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LTC4215-1/LTC4215-3

421513fc

Hot Swap Controller with

C Compatible Monitoring

Live Board Insertion

Electronic Circuit Breakers

Computers, Servers

Platform Management

Allows Safe Insertion into Live Backplane

8-Bit ADC Monitors Current and Voltage

C/SMBus Interface

Wide Operating Voltage Range: 2.9V to 15V

dI/dt Controlled Soft-Start

Circuit Breaker Timeout: 20μs (LTC4215-1) or

420μs (LTC4215-3)

Three General Purpose Outputs

High Side Drive for External N-channel MOSFET

No External Gate Capacitor Required

Input Overvoltage/Undervoltage Protection

Optional Latchoff or Auto-Retry After Faults

Alerts Host After Faults

Inrush Current Limit with Foldback

Available in 24-Pin (4mm × 5mm) QFN

The LTC

4215-1/LTC4215-3 Hot Swap™ controllers allow

a board to be safely inserted and removed from a live

backplane. Using an external N-channel pass transistor,

board supply voltage and inrush current are ramped up at

a n a d j u s t a b l e r a t e . A n I

C interface and onboard ADC allow

for monitoring of load current, voltage and fault status.

The device features adjustable foldback current limit and

a soft-start pin that sets the dI/dt of the inrush current.

An I

C interface may conﬁ gure the part to latch off or

automatically restart after the LTC4215-1/LTC4215-3

detect a current limit fault.

The controller has additional features to interrupt the host

when a fault has occurred, provide three general purpose

outputs, notify when output power is good, detect insertion

of a load card, and power-up either automatically upon

insertion or wait for an I

C command to turn on.

The LTC4215-1 has a 20µs circuit breaker ﬁ lter for applica-

tions that require a fast fault response time. The LTC4215-3

has an extended 420µs circuit breaker ﬁ lter for applications

where supply transients may exceed 20µs.

UV V

SENSE

–

LTC4215-1

GATE

TIMER SSON

INTV

POWERGOOD

RESET

OK LED

MEASURED

VOLTAGE

GND EN

SOURCE

SDAI

SDAO

SCL

ADR0

ADR1

GPIO1

GPIO2

GPIO3

ADIN

3.4k

PLUG-IN

CARD

1.18k

P6KE16A

10Ω

0.005Ω

FDC653N

30.1k

OUT

12V

3.57k

4215 TA01a

0.1µF

CONNECTOR 2

CONNECTOR 1

34.8k

BACKPLANE

68nF

0.1µF

GND

SCL

SDA

12V

12V Application With 5A Circuit Breaker Start-Up Waveform

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

OUT

10V/DIV

GPIO1

10V/DIV

INRUSH

CURRENT

2.5A/DIV

10V/DIV

40ms/DIV

42151 TA01b

= 12000µF

5k PULL-UP TO V

CONTACT

BOUNCE

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other

trademarks are the property of their respective owners. Protected by U.S. Patent 7330065.

Summary of content (28 pages)

PAGE 1
LTC4215-1/LTC4215-3 Hot Swap Controller with I2C Compatible Monitoring FEATURES DESCRIPTION n The LTC®4215-1/LTC4215-3 Hot Swap™ controllers allow a board to be safely inserted and removed from a live backplane. Using an external N-channel pass transistor, board supply voltage and inrush current are ramped up at an adjustable rate. An I2C interface and onboard ADC allow for monitoring of load current, voltage and fault status.
PAGE 2
LTC4215-1/LTC4215-3 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) SOURCE GATE SENSE– SENSE+ VDD TOP VIEW 24 23 22 21 20 UV 1 19 FB OV 2 18 GPIO1 SS 3 17 INTVCC 25 GND 4 16 TIMER ON 5 15 ADIN EN 6 14 GPIO3 13 ADR1 ADR0 NC 9 10 11 12 GPIO2 8 SCL SDAO 7 SDAI Supply Voltage (VDD) ................................ –0.3V to 24V Supply Voltage (INTVCC) .......................... –0.3V to 6.5V Input Voltages GATE-SOURCE (Note 3) .......................... –0.
PAGE 3
LTC4215-1/LTC4215-3 ELECTRICAL CHARACTERISTICS The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. VDD = 12V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS l VDD(HYST) Input Supply Undervoltage Lockout Hysteresis 75 100 125 mV INTVCC Internal Regulator Voltage VDD ≥ 3.3V l 2.9 3.1 3.4 V INTVCC(UVL) INTVC Undervoltage Lockout INTVCC Rising l 2.55 2.64 2.
PAGE 4
LTC4215-1/LTC4215-3 ELECTRICAL CHARACTERISTICS The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. VDD = 12V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Other Pin Functions VGPIO1(OL) GPIO1 Pin Output Low Voltage IGPIO1 = 5mA l 0.25 0.4 V VGPIO2(OL) GPIO2 Output Low Voltage IGPIO2 = 3mA l 0.2 0.4 V VGPIO3(OL) GPIO3 Output Low Voltage IGPIO3 = 1mA l 0.2 0.
PAGE 5
LTC4215-1/LTC4215-3 ELECTRICAL CHARACTERISTICS The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. VDD = 12V unless otherwise noted. SYMBOL PARAMETER CONDITIONS l VSDA,SCL(TH) SDA, SCL Input Threshold ISDA,SCL(OH) SDA, SCL Input Current SCL, SDA = 5V l VSDA(OL) SDA Output Low Voltage ISDA = 3mA l Operates with fSCL ≤ fSCL(MAX) l MIN TYP MAX 1.3 1.7 1.9 V ±1 μA 0.4 V 0.
PAGE 6
LTC4215-1/LTC4215-3 TYPICAL PERFORMANCE CHARACTERISTICS VTH(UV) vs Temperature TA = 25°C, VDD = 12V unless otherwise noted. VHYST(UV) vs Temperature 1.240 ITIMER vs Temperature 90 110 85 105 1.236 1.234 ITIMER (μA) VHYST(UV) (mV) VTH (UV) RISING (V) 1.238 80 75 1.232 1.230 –50 –25 50 25 0 TEMPERATURE (°C) 95 70 –50 100 75 –25 50 25 0 TEMPERATURE (°C) 10 5 0 0.2 0.6 0.4 0.8 1.0 1.2 26 VDD = 5V, 12V VDD = 3.3V 25 24 10 1 23 22 –50 1.
PAGE 7
LTC4215-1/LTC4215-3 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD = 12V unless otherwise noted. Total Unadjusted Error vs Code (ADIN) VOL(GPIO1) vs IGPIO1 0.6 0.006 0.5 0.005 ADC INL vs Code (ADIN) 0.5 VDD = 3.3V, 5V, 12V 0.3 0.3 0.2 0.004 INL (LSB) ERROR (mV) 0.4 0.003 0.2 0.002 0.1 0.001 0 0 0.1 0 –0.1 –0.2 –0.3 –0.4 2 4 6 IGPIO1 (mA) 8 10 –0.5 0 64 4215 G12 128 CODE 256 192 0.5 1.0 0.4 0.8 0.3 0.6 0.2 0.1 0 –0.1 –0.2 –0.3 256 4215 G14 0 –0.2 –0.4 –0.6 –0.8 –1.
PAGE 8
LTC4215-1/LTC4215-3 PIN FUNCTIONS ADIN: ADC Input. A voltage between 0V and 1.235V applied to this pin is measured by the onboard ADC. Tie to ground if unused. ADR0, ADR1: Serial Bus Address Inputs. Tying these pins to ground, to the INTVCC pin or leaving open conﬁgures one of 9 possible addresses. See Table 1 in Applications Information. EN: Enable Input. Ground this pin to indicate a board is present and enable the N-channel MOSFET to turn on. When this pin is high, the MOSFET is not allowed to turn on.
PAGE 9
LTC4215-1/LTC4215-3 PIN FUNCTIONS OV: Overvoltage Comparator Input. Connect this pin to an external resistive divider from VDD. If the voltage at this pin rises above 1.235V, an overvoltage fault is detected and the GATE turns off. Tie to GND if unused. SCL: Serial Bus Clock Input. Data at the SDA pin is shifted in or out on rising edges of SCL. This is a high impedance pin that is generally driven by an open-collector output from a master controller.
PAGE 10
LTC4215-1/LTC4215-3 FUNCTIONAL DIAGRAM SENSE– VCC 10μA FOLDBACK AND dI/dt SS 1.235V 0.6V FB 1.235V UV 0.4V OV INTVCC 1.235V 10μA 1.235V EN ON 1.235V 2.84V VDD 15.6V + – + – OV1 + – + – FAULT UV RST RESET + – + – –+ – + +– GATE CS CHARGE PUMP AND GATE DRIVER SOURCE 75mV 25mV FET ON UV + – + – CB SENSE+ 1.235V PG + – PWRGD GP LOGIC EN ON GP ON UVLO1 VDD(UVLO) OV2 GPI03 1.6V OV GP EN + – TM1 OV2 TM2 + – + – + – + – GPI02 1.6V GPI01 1V 0.
PAGE 11
LTC4215-1/LTC4215-3 OPERATION The LTC4215-1/LTC4215-3 are designed to turn a board’s supply voltage on and off in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. During normal operation, the charge pump and gate driver turn on an external N-channel MOSFET’s gate to pass power to the load. The gate driver uses a charge pump that derives its power from the VDD pin. Also included in the gate driver is an internal 6.5V GATEto-SOURCE clamp.
PAGE 12
LTC4215-1/LTC4215-3 APPLICATIONS INFORMATION A typical LTC4215-1/LTC4215-3 application is in a high availability system in which a positive voltage supply is distributed to power individual cards. The device measures card voltages and currents and records past and present fault conditions. The system queries each LTC4215-1/ LTC4215-3 over the I2C periodically and reads status and measurement information. Several conditions must be present before the external MOSFET turns on.
PAGE 13
LTC4215-1/LTC4215-3 APPLICATIONS INFORMATION The MOSFET is turned on by charging up the GATE with a 20μA current source. When the GATE voltage reaches the MOSFET threshold voltage, the MOSFET begins to turn on and the SOURCE voltage then follows the GATE voltage as it increases. When the MOSFET is turning on, it ramps inrush current up linearly at a dI/dt rate selected by capacitor CSS.
PAGE 14
LTC4215-1/LTC4215-3 APPLICATIONS INFORMATION (OV pin), input undervoltage (UV pin), overcurrent circuit breaker (SENSE– pin), or EN transitioning high. Writing a logic one into the UV, OV or OC fault bits (D0-D2 in Table 5) also latches off the GATE if their auto-retry bits are set to false. The GATE pin is then brought down and regulated in order to limit the current sense voltage to 75mV.
PAGE 15
LTC4215-1/LTC4215-3 APPLICATIONS INFORMATION Board Present Change of State Whenever the EN pin toggles, bit D4 is set to indicate a change of state. When the EN pin goes high, indicating board removal, the GATE turns off immediately (with a 1mA current to ground) and clears the board present bit, C4. If the EN pin is pulled low, indicating a board insertion, all fault bits except D4 are cleared and enable bit, C4, is set.
PAGE 16
LTC4215-1/LTC4215-3 APPLICATIONS INFORMATION Once the GPIO2 signal has been released for one fault, it is not pulled low again until the FAULT register indicates a different fault has occurred or the original fault is cleared and it occurs again. Note that this means repeated or continuing faults do not generate alerts until the associated FAULT register bit has been cleared. The GPIO2 pin may also be used as a general purpose output by setting or resetting bit D6.
PAGE 17
LTC4215-1/LTC4215-3 APPLICATIONS INFORMATION Current Limit Stability Supply Transients For many applications the LTC4215-1/LTC4215-3 current limits will be stable without additional components. However there are certain conditions where additional components may be needed to improve stability. The dominant pole of the current limit circuit is set by the capacitance and resistance at the gate of the external MOSFET, and larger gate capacitance makes the current limit loop more stable.
PAGE 18
LTC4215-1/LTC4215-3 APPLICATIONS INFORMATION large changes in current ﬂowing through power supply traces may cause inductive voltage spikes which exceed 24V. To minimize such spikes, the power trace inductance should be minimized by using wider traces or heavier trace plating. Also, a snubber circuit dampens inductive voltage spikes. Build a snubber by using a 100Ω resistor in series with a 0.1μF capacitor between VDD and GND.
PAGE 19
LTC4215-1/LTC4215-3 APPLICATIONS INFORMATION 1.235V/R3 at the edge of the OV rising threshold, where ISTRING > 40μA. Then solve the following equations: R2 = R1 = VOV(OFF) VUV(ON) • R3 • UVTH(RISING) – R3 OVTH(FALLING) VUV(ON) • (R3+R2) UVTH(RISING) – R3 – R2 In our case we choose R3 to be 3.4k to give a resistor string currrent below 100μA. Then solving the equations results in R2 = 1.16k and R1 = 34.6k. The FB divider is solved by picking R8 and solving for R7, choosing 3.
PAGE 20
LTC4215-1/LTC4215-3 APPLICATIONS INFORMATION I2C Device Addressing write address that writes to all LTC4215-1/LTC4215-3s, regardless of their individual address settings. Mass write can be disabled by setting register bit A4 to zero. Address (0001 100) is the SMBus Alert Response Address. If the LTC4215-1/LTC4215-3 are pulling low on the GPIO2 pin due to an alert, it acknowledges this address by broadcasting its address and releasing the GPIO2 pin.
PAGE 21
LTC4215-1/LTC4215-3 APPLICATIONS INFORMATION Acknowledge The acknowledge signal is used in handshaking between transmitter and receiver to indicate that the last byte of data was received. The transmitter always releases the SDA line during the acknowledge clock pulse. When the slave is the receiver, it pulls down the SDA line so that it remains LOW during this pulse to acknowledge receipt of the data.
PAGE 22
LTC4215-1/LTC4215-3 APPLICATIONS INFORMATION Address, the LTC4215-1/LTC4215-3 respond with their address on the SDA line and then release GPIO2 as shown in Figure 11. The GPIO2 line is also released if the device is addressed by the bus master. The GPIO2 signal is not pulled low again until the FAULT register indicates a different fault has occurred or the original fault is cleared and it occurs again.
PAGE 23
LTC4215-1/LTC4215-3 APPLICATIONS INFORMATION Table 2.
PAGE 24
LTC4215-1/LTC4215-3 APPLICATIONS INFORMATION Table 4.
PAGE 25
LTC4215-1/LTC4215-3 TYPICAL APPLICATIONS 5V Card Resident Application with Inverting LED Driver and 16.6A Circuit Breaker RS 0.0015Ω VIN 5V Q1 Si7880DP + CF 0.1μF R1 11.5k 1% R2 1.74k 1% R3 2.67k 1% SDA SCL ALERT R5 10Ω BACKPLANE PLUG-IN CARD R8 2.67k 1% C1 22nF UV VDD OV SDAI SDA0 SCL GPIO2 SENSE GATE LTC4215-1 ON INTVCC ADR0 ADR1 TIMER GND R7 6.98k 1% R6 15k C3 0.
PAGE 26
LTC4215-1/LTC4215-3 TYPICAL APPLICATIONS 12V Application with High Current Non-Inverting LED Drivers and 8.3A Circuit Breaker RS 0.003Ω Q1 12V + CONNECTOR 1 CONNECTOR 2 R1 34.8k 1% P6KE16A SDA SCL R2 1.18k 1% 0.1ΩF R3 3.47k 1% CL R5 10Ω UV VDD SENSE+ SENSE– GATE SOURCE FB OV SDAI GPIO3 SDAO LTC4215-1 GPIO2 SCL GPIO1 ADR0 ADR1 ON INTVCC TIMER SS C3 0.1μF GND BACKPLANE PLUG-IN CARD VOUT 12V R7 30.1k 1% R8 3.57k 1% R9 24k RESET 3.
PAGE 27
LTC4215-1/LTC4215-3 PACKAGE DESCRIPTION UFD Package 24-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1696 Rev A) 0.70 ±0.05 4.50 ± 0.05 3.10 ± 0.05 2.00 REF 2.65 ± 0.05 3.65 ± 0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 3.00 REF 4.10 ± 0.05 5.50 ± 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 ± 0.10 (2 SIDES) R = 0.05 TYP 2.00 REF R = 0.115 TYP 23 0.75 ± 0.05 PIN 1 NOTCH R = 0.20 OR C = 0.35 24 0.40 ± 0.
PAGE 28
LTC4215-1/LTC4215-3 TYPICAL APPLICATION –12V Card Resident Application with Optically Isolated I2C and 16.6A Current Limit RS 0.0015Ω Q1 Si7880DP OUTPUT GND –7V R10 3.3k R9 10k –7V 5V 2 8 7 6 CF 0.1μF 3 HCPL-0300 5 R1 34.8k 1% R5 10Ω R2 1.18k 1% R6 15k R3 3.4k 1% –12V SDA R4 3.3k D2 P6KE16A 6 8 SCL –7V SOURCE FB GPIO1 GPIO2 LTC4215-1 GPIO3 R7 30.1k 1% R8 3.57k 1% –12V CL 1000μF ADIN ADR0 ADR1 EN GND TIMER C3 0.1μF R12 10k R13 3.