Datasheet

LTC4156
42
4156f
The generalized form of the NTC equations provided in
the Operations section are included above to facilitate
interpretation of the thermistor analog to digital converter
results using the custom bias network. If only R
BIAS
was
modified, let
α
TEMP_RANGE
= 0.
Choosing the Input Multiplexer/Overvoltage
Protection MOSFETs
The LTC4156 contains an internal charge pump voltage
doubler to drive N-channel MOSFETS via the USBGT and
WALLGT pins. The gate-source voltage available to drive
the input multiplexer/protection FETS is approximately
equal to the input voltage, typically 4V to 6V. To ensure
that the FET channels are sufficiently enhanced to provide
a low resistance conduction
path, the FET threshold volt-
age should be less than approximately 2.5V. Total gate
leakage current should be below 1µA to guarantee ample
charge pump output voltage. The gate oxide breakdown
voltage should be higher than 7V. The FET R
DS(ON)
will
negatively impact the switching regulator and battery
charger efficiency at high current levels. With two protec-
tion FETs in series (MN1 and MN3, MN2
and MN4), the
total resistance is the sum of the individual R
DS(ON)
s. This
combined resistance should be negligible compared to the
typical 80mΩ to 90mΩ resistance of the LTC4156 internal
switches for maximum performance. The drain breakdown
voltage of devices MN1 and MN2 must be appropriate for
the level of overvoltage protection desired. The drains will
be exposed to the full magnitude of applied
input voltage.
The drains of devices MN3 and MN4 are exposed only to
the operating voltage range of the LTC4156. Therefore
the drain breakdown voltage of devices MN3 and MN4
should be rated for at least 7V. Table 35 lists several suit-
able N-channel transistors. Transistors with lower BV
DSS
may be appropriate for devices MN3 and MN4 if reverse
protection is not required. Note that resistors
R1 and R2
must also be sized appropriately for power dissipation
based on the level of overvoltage protection desired, as
explained in the Operation section.
Table 35. Recommended N-Channel Input Multiplexer MOSFETs
MANUFACTURER
PART
NUMBER
R
DS(ON)
(mΩ) V
T
(V) BV
DSS
(V)
Fairchild FDMC8651 4.3 1.1 30
Fairchild FDMC8030 10.7 2.8 40
Vishay Si7938DP 5.6 2.5 40
APPLICATIONS INFORMATION
α
T
=
k
SPAN
• NTCVAL + k
OFFSET
1−k
SPAN
• NTCVAL – k
OFFSET






α
BIAS
− α
TEMP_RANGE
T =
b
ln
k
SPAN
• NTCVAL + k
OFFSET
1−k
SPAN
• NTCVAL – k
OFFSET






α
BIAS
− α
TEMP_RANGE






+
b
T
0
Figure 10. Dual-Input Overvoltage Protection
V
BUS
TO USB
INPUT
TO WALL
INPUT
OVGCAP
USBGT
USBSNS
WALLGT
LTC4156
WALLSNS
4156 F10
MN1
R1
R2
MN3
MN2 MN4