Datasheet

LTC4155
44
4155fc
Figure 11. Single-Input Overvoltage Protection
Figure 12. Dual-Input Positive and Negative Voltage Protection
the drain breakdown voltage rating of MN3 and MN4 and
negative protection down to the drain breakdown volt-
age rating of MN1 and MN2. Q1 and Q2 are small-signal
transistors to protect the gate oxides of MN1 and MN2.
Note that it is necessary to orient the N-channel MOSFETs
with the drain connections common and the source/body
connections to the input connector and the V
BUS
pin.
level, but the inductor current will increase rapidly to the
LTC4155’s peak current clamp as incremental inductance
tends toward zero. If an overload condition persists with
a small inductor, it is possible that the inductor could be
damaged by its own resistive temperature rise.
The inductor core should be made from a material such as
ferrite, suitable for switching at 2.25MHz without excessive
hysteretic losses. Table 37 lists several suitable inductors.
Table 37. Recommended Inductors
MANUFACTURER PART NUMBER
R
DC
(mΩ)
I
MAX
(A)
PACKAGE
(mm)
Vishay IHLP2525AHE-B1ROMO1 17.5 7
6.5 × 6.9 × 3.2
Coilcraft XFL4020-102ME 10.8 5.4
4 × 4 × 2.1
TDK TDKLTF5022T1R2N4R2-LF 21 4.2
5 × 5.2 × 2.2
I
MAX
is the lower of the typical 30% saturation current and self-heating
current specifications.
Choosing the Battery Charger MOSFETs
The LTC4155 requires a single external P-channel MOS-
FET connected between the CHGSNS and BATSNS pins
to conduct battery charge and ideal diode currents. The
threshold voltage magnitude should be less than approxi-
mately 2.5V. (The P-channel threshold might be expressed
as a negative number, V
GS(th)
, or as a positive number
V
SG(th)
). Gate leakage current should be below 500nA.
Drain voltage breakdown and gate oxide breakdown volt-
ages should both be above 5V in magnitude. The LTC4155
contributes approximately 40m resistance in the current
sense circuitry in series with the battery charger FET.
Channel resistance, R
DS(ON)
, should be small relative to
the 40m for maximum efficiency both charging the bat-
tery and delivering power from the battery to the system
load. Table 38 lists several suitable P-channel transistors.
Optionally, a second P-channel MOSFET may be con-
nected in series with the first if the application requires
that power be cut off from any downstream devices on
V
OUT
in low power ship-and-store mode. Further details
about low power ship-and-store mode may be found in
the Operation section. The requirements for the second
device are the same as those enumerated above, with the
caveats that total gate leakage current is the sum of the
individual leakage currents and total R
DS(ON)
is the sum
of the individual R
DS(ON)
s.
APPLICATIONS INFORMATION
V
BUS
TO POWER
INPUT
OVGCAP
USBGT
USBSNS
WALLGT
LTC4155
WALLSNS
4155 F11
R1
MN1
V
BUS
TO USB
INPUT
TO WALL
INPUT
OVGCAP
USBGT
USBSNS
WALLGT
LTC4155
WALLSNS
4155 F12
MN1
R5
47k
R6
47k
C1
OPT
0.01µF
R3 5M
R4 5M
R1 3.6k
R2 3.6k
MN3
MN2 MN4
Q1
Q2
Q3
Q4
Choosing the Inductor
The LTC4155 is designed to operate with a 1µH inductor,
with core saturation, winding resistance, and thermal
rise characteristics appropriate for the application’s peak
currents. The inductor current ripple magnitude is ap-
proximately 400mA under normal conditions, resulting
in a peak inductor current 200mA higher than the aver-
age output current of the switching regulator. The aver-
age output current of the step-down regulator is higher
than the average input current by the ratio V
BUS
/V
OUT,
neglecting efficiency losses. The LTC4155 can tolerate
transient excursions beyond the inductor’s core saturation