Datasheet

LTC4155
17
4155fc
Table 2. I
2
C Map
REGISTER ACCESS
SUB
ADDRESS D7 D6 D5 D4 D3 D2 D1 D0
REG0 WRITE/
READBACK
0x00
DISABLE
INPUT
UVCL
ENABLE
BATTERY
CONDI-
TIONER
LOCKOUT
USB OTG ID
PIN
USB CURRENT LIMIT
REG1 WRITE/
READBACK
0x01 INPUT
PRIORITY
SAFETY TIMER WALL CURRENT LIMIT
REG2 WRITE/
READBACK
0x02
CHARGE CURRENT FLOAT VOLTAGE C/x DETECTION
REG3 READ 0x03
CHARGER STATUS
ID PIN
DETECTION
STATUS
BOOST
ENABLE
STATUS
THERMISTOR STATUS
LOW
BATTERY
STATUS
REG4 READ 0x04
EXTERNAL
POWER
GOOD
USBSNS
GOOD
WALLSNS
GOOD
INPUT
CURRENT
LIMIT
ACTIVE
INPUT UVCL
ACTIVE
OVP ACTIVE OTG FAULT
BAD CELL
FAULT
REG5 READ 0x05
THERMISTOR VALUE
THERMIS-
TOR
WARNING
REG6 WRITE/
READBACK
CLEAR
INTERRUPT*
DISARM
SHIP-AND-
STORE
MODE*
0x06
ENABLE
CHARGER
INTERRUPTS
ENABLE
FAULT
INTERRUPTS
ENABLE
EXTERNAL
POWER
INTERRUPTS
ENABLE
USB OTG
INTERRUPTS
ENABLE
INPUT
CURRENT
LIMIT
INTERRUPTS
ENABLE
INPUT UVCL
INTERRUPTS
ENABLE
USB
On-The-Go
0
RESERVED
REG7 WRITE
ARM SHIP-
AND-STORE
MODE**
0x07
0
REQUIRED
0
REQUIRED
0
REQUIRED
0
REQUIRED
0
REQUIRED
0
REQUIRED
0
REQUIRED
0
REQUIRED
*Interrupts are cleared and ship-and-store mode is disarmed during the acknowledge clock cycle following a full data byte written to sub address 0x06.
Reading data from sub address 0x06 has no effect.
**Ship-and-store mode is armed during the acknowledge clock cycle following a full data byte written to sub address 0x07. The data written to sub
address 0x07 is ignored. Reading from sub address 0x07 has no effect and the returned data is undefined, independent of the arming state of
ship-and-store mode.
OPERATION
I
2
C