Datasheet

LTC4150
6
4150fc
BLOCK DIAGRAM
+
–
–
+
–
+
AMPLIFIER
C
F
+
C
F
SENSE
+
V
DD
R
SENSE
I
BAT
C
F
–
SENSE
–
2k
2k
200k
200k
100pF
200k
S2
S1
S3
SHDN
CONTROL
LOGIC
POLARITY
DETECTION
OFLOW/
UFLOW
REFHI
1.7V
REFLO
0.95V
CLR
POL
DISCHARGE
CHARGE
INT
GND
LOADCHARGER
COUNTER
UP/DN
R
SQ
4150 F01
8
1
3
4
2
7
10
9
6
5
Figure 1. Block Diagram
TIMING DIAGRAMS
t
CLR
4150 F02
50%
CLR
INT
50%
t
INT
4150 F03
50%
INT
50%
Figure 2. CLR Pulse Width to Reset INT,
CLR and INT Not Connected
Figure 3. INT Minimum Pulse Width, CLR and INT Connected