LTC4110 Battery Backup System Manager FEATURES DESCRIPTION n The LTC®4110 is a complete single chip, high efficiency, flyback battery charge and discharge manager with automatic switchover between the input supply and the backup battery or super capacitor. The IC provides four modes of operation: battery backup, battery charge, battery calibration and shutdown.
LTC4110 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) DCHFET CHGFET VDD BATID NC DCOUT INID TOP VIEW 38 37 36 35 34 33 32 DCIN 1 31 BAT CLN 2 30 SELC CLP 3 29 ISENSE ACPDLY 4 28 SGND 27 CSN DCDIV 5 SHDN 6 26 CSP 39 SDA 7 25 ITH SCL 8 24 ICHG GPI01 9 23 ICAL GPI02 10 22 IPCC GPI03 11 21 THB 20 THA SELA 12 TYPE TIMER VREF VCAL VCHG VDIS 13 14 15 16 17 18 19 ACPb DCIN, BAT, DCOUT, DCDIV, SHDN to GND ....................................................... –0.
LTC4110 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Unless otherwise specified, VDCIN = VDCOUT = VDCDIV = 12V, VBAT = 8.4V, GND = SGND = CLP = CLN = SHDN = 0V and RVREF = 49.9k. All currents into device pins are positive and all currents out of device pins are negative. All voltages are referenced to GND, unless otherwise specified.
LTC4110 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Unless otherwise specified, VDCIN = VDCOUT = VDCDIV = 12V, VBAT = 8.4V, GND = SGND = CLP = CLN = SHDN = 0V and RVREF = 49.9k. All currents into device pins are positive and all currents out of device pins are negative. All voltages are referenced to GND, unless otherwise specified.
LTC4110 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Unless otherwise specified, VDCIN = VDCOUT = VDCDIV = 12V, VBAT = 8.4V, GND = SGND = CLP = CLN = SHDN = 0V and RVREF = 49.9k. All currents into device pins are positive and all currents out of device pins are negative. All voltages are referenced to GND, unless otherwise specified.
LTC4110 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. Unless otherwise specified, VDCIN = VDCOUT = VDCDIV = 12V, VBAT = 8.4V, GND = SGND = CLP = CLN = SHDN = 0V and RVREF = 49.9k. All currents into device pins are positive and all currents out of device pins are negative. All voltages are referenced to GND, unless otherwise specified.
LTC4110 TYPICAL PERFORMANCE CHARACTERISTICS Output Charging Characteristics Showing Constant Current and Constant Voltage Operation Typical CHGFET and DCHFET Waveforms Supply Current vs DCIN Voltage in Idle Mode 1200 2.5 CC 1000 2.0 IBAT (mA) IDCIN (mA) 800 5V/DIV 600 CV 400 0V PRE-CHARGE 4110 G01 500ns/DIV 0 0 2 4 1.0 0.5 200 VIN = 12V VBAT = 12V (NiMH) 1.
LTC4110 PIN FUNCTIONS DCIN (Pin 1): External DC Power Sense Input. Provides a control input and supply for the main supply ideal diode function. CLN (Pin 2): Current Limit Sense Negative Input. See CLP pin. CLP (Pin 3): Current Limit Sense Positive Input. This pin and the CLN pin form a differential input that senses voltage on an external resistor for reverse current entering the power source while in low loss calibration mode. Should the current approach reversal, this function will terminate calibration.
LTC4110 PIN FUNCTIONS ACPb (Pin 13): AC Present Status Digital Output. OpenDrain N-MOSFET output is asserted low when the main supply is present as detected by the DCDIV pin and internal DCIN UVLO. VDIS (Pin 14): Battery Discharge Voltage Limit During Backup Program Input. Battery threshold voltage at which backup mode will terminate by turning off the isolation P-MOSFET with the BATID pin. Adjustable from external resistor string biased from VREF pin. For default threshold connect to GND pin.
LTC4110 PIN FUNCTIONS BAT (Pin 31): Battery Voltage Sense Input. This pin is used to monitor the battery and control charging voltage through an internal resistor divider connected to this pin that is disconnected in shutdown mode. Also provides a control input for battery ideal diode functions. Pin should be Kelvinconnected to battery to avoid voltage drop errors. DCHFET (Pin 32): Drives the Gate of an External N-MOSFET.
LTC4110 BLOCK DIAGRAM 37 DCOUT 36 NC SUPPLY INPUT BATTERY PowerPath CONTROLLER INID 38 35 BATID DCIN 1 31 BAT VDD 34 VDD REGULATOR NUMBER OF CELLS CA + – GND 39 27 CSN 26 CSP PRECISION VOLTAGE DIVIDER CHG/DCH SWITCH CURRENT SELECTION 22 IPCC + – EA CLP 3 CURRENT SWITCH 1.
LTC4110 OPERATION OVERVIEW In the typical application, the LTC4110 is placed in series with main power supply that powers all or part of the system, which must include the device(s) or system that needs battery backup.
LTC4110 OPERATION and ranges. It should be noted that even if the LTC4110 TYPE pin is not set to a smart battery mode, any SMBus commands sent by a host or a smart battery are still acted upon. For SuperCap support, see the Applications Information section. BATTERY BACKUP MODE Figure 1 shows the LTC4110 in backup mode and the corresponding PowerPath enabled. The LTC4110 use the DCDIV pin to typically monitor the DCIN voltage through an external resistor divider.
LTC4110 OPERATION SYSTEM LOAD BACKUP LOAD DCIN ON OFF OFF BATTERY CURRENT FLOW INID LTC4110 BATID CHGFET DCHFET 4110 F02 Figure 2. Charge Mode Operation for the battery chemistry selected. Specifically the TIMER pin becomes active and used to detect faults conditions or terminate the charge cycle itself as needed. Smart battery SMBus charge control commands are still honored if any are sent at any time.
LTC4110 OPERATION PWM STOPPED (BATTERY OVP) 14 15 ANY CHARGE STATE 10 RESET RESUME CHARGE STATE ANY CHARGE STATE 7, 12, 13 11 (BATTERY NEEDS RECHARGE) 1 5 (PRE-CONDITIONING FAULT) PRE-CONDITIONING CHARGE STOP CHARGE 6 (BULK TIME FAULT) 8 9 STOP CHARGE (OVERTEMPERATURE) 2 BULK CHARGE 3 4 (BATTERY FULL) TOP-OFF CHARGE 4110 F03 Figure 3.
LTC4110 OPERATION When the battery voltage exceeds the bulk charge threshold (VBC), the charger begins the bulk charge portion of the charge cycle. As the battery accepts charge, the voltage increases. Constant-current charge continues until the battery approaches the constant voltage. At this time, the charge current will begin to drop, signaling the beginning of the constant-voltage portion of the charge cycle.
LTC4110 OPERATION PWM STOPPED (BATTERY OVP) 11 12 ANY CHARGE STATE 1 WAKE UP CHARGE RESUME CURRENT STATE 8 10 RESET ANY CHARGE STATE 2 4, 7, 13, 14 PRE-CONDITIONING CHARGE 3 9 OFF (OVERTEMPERATURE) BULK CHARGE OFF 4 (BATTERY FULL) 5 (BAD BATTERY) 6 (BATTERY RECHARGE REQUEST) 4110 F04 Figure 4.
LTC4110 OPERATION SMBUS WAKE-UP CHARGE STATE The battery will be charged with a fixed “wake-up” current regardless of previous ChargingCurrent() and ChargingVoltage() register values during wake-up charging. The current is identical to the preconditioning charge current which is programmed with an external resistor through the IPCC pin. The wake-up timer has the same period as tTIMEOUT , typically 175sec (see tTIMEOUT).
LTC4110 OPERATION • The SafetySignal is registering RES_OR. Charge is stopped. The LTC4110 enters the reset state. • The AC power is no longer present (DCDIV < VAC or DCIN < UVLO). The LTC4110 enters the reset state. • • ALARM_INHIBITED is set in the ChargerStatus() register. Charge is stopped. The LTC4110 enters the SMBus OFF state. CHARGE_INHIBIT is set in the BBuControl() register. Charge is stopped, however, the T/4 timer is not paused.
LTC4110 OPERATION • The CAL_START bit in the BBuControl() register is set. The LTC4110 enters the calibration state. charger pauses until the voltage drops below the hysteresis (VBOVH). No fault is indicated. • The battery thermistor is registering RES_OR. The LTC4110 enters the reset state. An optional external NTC thermistor network can be used to provide an adjustable negative TC for the float voltage, monitor battery temperature and to detect battery presence.
LTC4110 OPERATION PWM STOPPED (BATTERY OVP) RESET 7 8 ANY CHARGE STATE 2 1 RESUME CHARGE STATE ANY CHARGE STATE 4 CHARGE 9 STOP 3 4110 F05 5 6 STOP (OVERTEMPERATURE) Figure 5.
LTC4110 OPERATION system load not be adequate to absorb the current. The primary protection is accomplished with an external current sense resistor (RCL), connected between the CLP and CLN pins, through which the system load current flows. When the voltage across the resistor reaches 10mV (IBDT) or less, representing a low forward current, calibration mode is terminated. The current protection can be completely disabled by connecting both CLP and CLN pins to GND.
LTC4110 OPERATION RESUME STATE 4 (CALIBRATION COMPLETED) ANY STATE 7 NO 8 (CALIBRATION FAULT) CALIBRATION MODE? 6, 9 CALIBRATION RUNNING 3 2 RESET 1 CALIBRATION START YES 5 (BATTERY IS DEAD) 4110 F07 Figure 7.
LTC4110 OPERATION The micropower shutdown state will be maintained if the DCIN supply is removed and sufficient battery voltage is present (VBAT ≥ 2.7V). When DCIN is reapplied as detected by the UVLO (see VUVI), regardless of the level of the SHDN pin, the shutdown state is automatically cancelled. Register reset state is cancelled until DCIN is reapplied as determined by the DCDIV pin.
LTC4110 OPERATION Where: VINT THA_SELB C = C rate of the battery RTHA 1.13k ICHG = Programmed charging current MUX THA For Example, if we charge a 3Ah battery with 1A current, then x = 15. HI_REF REF LO_REF VINT RTHB 54.
LTC4110 OPERATION The three I/O outputs, GPIO1, GPIO2 and GPIO3 are digital I/O pins with two modes of operation. There are a total of 5 status signals possible. CHGb, C/xb, BKUP-FLTb, CHG_FLTb, and CAL_COMPLETEb. Each of these signals is asserted low on the output when they are true. CHGb is an asserted low signal when either CHG_STATE_0 or CHG_STATE_1 is set to one. C/xb is asserted low signal when C/x state in the charge cycle is reached.
LTC4110 OPERATION Table 5c. GPIO2 Modes HOST PROGRAMMED BIT SETTINGS GPIO_2 MODE DATA NOTE GPIO_2_EN GPIO_2_OUT GPIO_2_BUFLT 0 0 0 Digital Input Input Data GPIO_2_IN 1 X 1 Status Output BKUP_FLTb With Pull-Up 1 0 0 Digital Output 0 With Pull-Up 1 1 0 Digital Output 1 With Pull-Up GPIO_2 MODE DATA NOTE Status Output BKUP_FLTb With Pull-Up GPIO_3 MODE DATA NOTE Table 5d. GPIO2 Power Up Mode (SELA = 0.
LTC4110 OPERATION processed to allow compliance with smart battery charge and discharge termination and protection control. However, there is no actual value processing of the voltage or current charge commands. IC will acknowledge all smart battery write commands, but process only a subset of them. Full SMBus error and reset handling is supported. The SMBus remains functional during backup mode, but not in SHDN mode.
LTC4110 OPERATION Table 6. Register Command Set Descriptions (XxxxXxxx() – Register Byte, XXXXXXXX – Status Bit) LABEL DESCRIPTION ChargerStatus() – Read Only. The SMBus host uses this command to read the LTC4110’s charge status bits. AC_PRESENT Set to 1 when sufficient input voltage (DCDIV > VAC + VACH and DCIN above UVLO) available and switches load from battery to main supply. Zero indicates backup mode engaged. BATTERY_PRESENT BATTERY_PRESENT is set if a battery is present, otherwise it is cleared.
LTC4110 OPERATION LABEL DESCRIPTION OVER_TEMP_ALARM Set to one indicates battery is temperature is out of range. Setting this bit will stop both a calibration process and a charging process (default = zero). TERMINATE_DISCHARGE_ALARM Set to one indicates battery requesting discharge termination. Smart battery only. Setting this bit will only stop a calibration process (default = zero). BBuStatus() – Read Only. The SMBus host uses this command to read the LTC4110’s status bits.
LTC4110 OPERATION LABEL DESCRIPTION GPIO_1_CHG Set to one sends an inverted CHG_ON (internal register, set to 1 when either CHG_STATE_0 or CHG_STATE_1 is set to 1) status signal out to the GPIO1 pin. If this bit is set, the value of CHG_ON overrides the value of the GPIO_1_ OUT bit state. Pin must be output enabled with GPIO_1_EN bit (default = set to zero/off) GPIO_2_BUFLT Set to one sends an inverted BKUP_FLT status signal out to the GPIO2 pin.
LTC4110 OPERATION Table 7.
LTC4110 APPLICATIONS INFORMATION The first configuration option to set for the LTC4110 is the type and cell count of the battery you wish to use. Pins TYPE and SELC are use to set this configuration. Please note NiMH and NiCd batteries are only supported in the smart battery configuration. The three state input pins SELA, SELC and TYPE should NOT be changed while power is applied to the IC unless in shutdown mode. Such action will result in unpredictable behavior from the LTC4110.
LTC4110 APPLICATIONS INFORMATION SOFT-START The LTC4110 is soft-started with the 0.1μF capacitor on the ITH pin. On start-up, the ITH pin voltage will rise quickly to 0.1V, then ramp up at a rate set by the internal 24μA pull-up current and the external capacitor. Battery charging current starts ramping up when ITH voltage reaches 0.7V and full current is achieved with ITH at about 2V. With a 0.
LTC4110 APPLICATIONS INFORMATION the highest current flow between charge and calibration modes, whichever is greater. R SNS(BAT) = 100mV IMAX Recommended starting values for the filter is: RCSP1 = RCSN1 between 1K and 2K RCSP1 + RCSP2 = RCSN1 + RCSN2 = about 3K CCSP = CCSN = about 3 • CITH. See Table 10 for example values. Figure 12 shows typical values for CITH = 0.
LTC4110 APPLICATIONS INFORMATION to monitor the primary current in both sides with a single RSNS(FET) resistor, both transformer windings must be connected prior to RSNS(FET). Since the secondary phase is always 180 degrees out of phase with the primary, the following current waveform in Figure 14 is the result. IPRI PRIMARY CURRENT 0 IPRI N SECONDARY CURRENT 4110 F14 Figure 14. RSNS(FET) Current Waveform The value of ripple current, ΔI, is a direct function of the transformer inductance.
LTC4110 APPLICATIONS INFORMATION PROGRAMMING CHARGE VOLTAGE β = exponential temperature coefficient of resistance Depending on the battery chemistry chosen by the TYPE pin, a charge termination voltage or a float voltage will be required. The difference between the two is time. A float voltage is applied to a battery forever. The VCHG pin is used to set any of these voltages and the equations remain the same. For this document, we will use the term float voltage generically.
LTC4110 APPLICATIONS INFORMATION VREF RCSP = RCSP1 + RCSP2 (1 – k3) • RVREF RCSN = RCSN1 + RCSN2 + – RICHG = resistor connected between ICHG pin and GND k3 • RVREF RIPCC = resistor connected between IPCC pin and GND RICAL = resistor connected between ICAL pin and GND. R2 R2 k2 = RSNS(BAT) = resistor between flyback transformer and battery VCHG R2 + R3 R3 THA If any programming resistor value on any of the three pins exceeds 100k, see Flyback Compensation section for more information.
LTC4110 APPLICATIONS INFORMATION R1 = resistor connected between DCDIV and GND R2 = resistor connected between supply input and DCDIV VBGR = reference voltage 1.220V For example, if supply input = 12V and backup starts when it drops to 11V, then VBACKUP = 11V, VBACKDRIVE = 13.5V, R2/R1 = 8.02, choose R1 = 10k, then R2 = 80.6k. If a higher ratio than VOVP/VBGR = 1.23 is desired between VBACKDRIVE and VBACKUP, a third resistor can be used as shown in Figure 17.
LTC4110 APPLICATIONS INFORMATION where VCUTOFF = adjusted cutoff threshold voltage VCAL/VDIS = voltage on VCAL or VDIS pin VBGR =1.220V The resistor divider connected to VREF pin will affect timer. See the Programming Charge Time with TIMER and VREF Pins section for more details. PROGRAMMING CHARGE TIME WITH TIMER AND VREF PINS Charge time limits for Li-Ion batteries can be programmed by selection of capacitance on the TIMER pin, but is dependent upon resistance on the VREF pin.
LTC4110 APPLICATIONS INFORMATION Avoid capacitors with high leakage currents. See the Programming Charge Time with TIMER and VREF Pins section for details concerning the VREF pin. For minimum delay open the ACPDLY pin. BAT PIN CURRENT IN IDLE MODE When LTC4110 is in IDLE mode (i.e.
LTC4110 APPLICATIONS INFORMATION Example: RCL: RCL power rating is a function of the maximum forward VDCIN = 12V, fOSC = 300kHz, QG1 = QG2 = 15nC, IQ = 3mA current the system load draws. See Figure 11. PD = 144mW Find a sense resistor who’s power rating is greater than PR(CL) SNUBBER DESIGN RSNS(BAT): RSNS(BAT) power rating is a function of the The values given in the applications schematics have been found to work quite well for this 12V-1A application.
LTC4110 APPLICATIONS INFORMATION The VDS ratings of the MOSFETs need to be higher than these values. The MOSFET current ratings for the primary side must be higher than IPRI, which is IPRI(CHG) or IPRI(CAL) for charge and Calibration mode respectively. See Equations 1 and 2. MOSFET current ratings for the secondary side must be higher than IPRI/N. Since both MOSFETs must perform both roles, the minimum current rating of the MOSFETs should be greater than the higher of these values.
LTC4110 APPLICATIONS INFORMATION that the power dissipated is never allowed to rise above the manufacturer’s recommended maximum level. Regardless of which way you go, we offer the following thoughts. Switching transition time is another consideration. When the LTC4110 senses a need to switch any PowerPath MOSFETs on or off time delays are encountered. MOSFETs with higher QGATE will require more bulk capacitance on DCOUT to hold up all the system’s power supply function during the transition.
LTC4110 APPLICATIONS INFORMATION INPUT AND OUTPUT CAPACITORS The LTC4110 uses a synchronous flyback regulator to provide high battery charging current. A chip ceramic capacitor is recommended for both the input and output capacitors because it provides low ESR and ESL and can handle the high RMS ripple currents. However, some Hi-Q capacitors may produce high transients due to self resonance under some start-up conditions, such as connecting the charger input to a hot power source.
LTC4110 APPLICATIONS INFORMATION OPERATION WITH DUAL BACKUP SYSTEMS DCIN TO BATTERY TRANSITION CHATTER REMOVAL If a dual backup system consisting of two LTC4110s each with its own backup battery is needed and a SMBus is used, each LTC4110 should be programmed by the SELA pin to have different addresses. If smart batteries with SMBus are used, a SMBus mux may be required to selectively address each battery. This mux may also be used to address the LTC4110. See SMBus Interface section for more information.
LTC4110 APPLICATIONS INFORMATION PCB LAYOUT CONSIDERATIONS Other Recommendations For maximum efficiency, the switch node rise and fall times should be minimized. To prevent magnetic and electrical field (EMI) radiation and high frequency resonant problems, proper layout of the components connected to the IC is essential. 6. Optionally use vias to connect power supply sources positive and negative (ground) connections from other copper layers to the flyback layout.
LTC4110 TYPICAL APPLICATIONS Battery Backup System Manager Controlling a Six-Series Cell SLA Battery with Temperature Compensation RCL 0.02Ω 1W SUPPLY INPUT (12V) INPUT IDEAL DIODE Q2 0.1μF LOW ESR 8.66k TO SYSTEM LOAD TO BACKUP LOAD 0.1μF LOW ESR Q3 BATTERY IDEAL DIODE 1.21k 20μF VERY LOW ESR INID DCIN DCOUT NC CLN BATID CLP CHGFET DCDIV 7.32k DCHFET THA 24.3k 25.5k VREF 1nF 33Ω 0.5W 5% Q1B Q1A RSNS(FET) 0.05Ω 0.5W RSL 3.32k ISENSE THB T1 1nF 33Ω 0.
LTC4110 TYPICAL APPLICATIONS Battery Backup System Manager Controlling a Nine-Series Cell NiMH Battery with Calibration Managed by Host Processor RCL 0.02Ω 1W SUPPLY INPUT (12V) INPUT IDEAL DIODE Q2 0.1μF LOW ESR 8.66k TO SYSTEM LOAD TO BACKUP LOAD 0.1μF LOW ESR Q3 BATTERY IDEAL DIODE 1.21k T1 INID DCIN DCOUT NC CLN 20μF VERY LOW ESR BATID CLP CHGFET DCDIV RTHA 1.13k DCHFET THA 330nF 2k 1k 2k 1k RSNS(BAT) 0.1Ω 0.25W CSP 49.9k CSN VCHG 36.5k 187k 37.4k 10.
1.21k 8.66k SUPPLY INPUT (12V) 0.1μF SMB1 37.4k 187k 36.5k RTHB 54.9k RTHA 1.13k 0.1μF LOW ESR Q1, Q2: Si7216DN Q3, Q4: Si7445DP Q5, Q6: Si7983DP T1, T2: BH510-1019 HOST I2C/SMBus + + + 20μF VERY LOW ESR RSNS(BAT) 0.1Ω 0.25W SMB1 RSNS(FET) 0.05Ω 0.5W Q1B 1nF 33Ω 0.5W 5% 10.8V 3 CELL SMBUS MULTIPLEXOR 10k NTC BATTERY 1 (12.6V) 113k SMB1 0.1μF SMB2 37.4k 187k 36.5k RTHB 54.9k RTHA 1.
LTC4110 PACKAGE DESCRIPTION UHF Package 38-Lead Plastic QFN (5mm × 7mm) (Reference LTC DWG # 05-08-1701) 0.70 p 0.05 5.50 p 0.05 5.15 ± 0.05 4.10 p 0.05 3.00 REF 3.15 ± 0.05 PACKAGE OUTLINE 0.25 p 0.05 0.50 BSC 5.5 REF 6.10 p 0.05 7.50 p 0.05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 p 0.10 0.75 p 0.05 PIN 1 NOTCH R = 0.30 TYP OR 0.35 s 45o CHAMFER 3.00 REF 37 0.00 – 0.05 38 0.40 p0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 2 5.15 ± 0.10 7.00 p 0.10 5.
LTC4110 TYPICAL APPLICATION Battery Backup System Manager Controlling a Three-Series Cell Li-Ion, Gas Gauge Smart Battery with Calibration Managed by Host Processor RCL 0.033Ω 0.5W SUPPLY INPUT (12V) TO SYSTEM LOAD 22μF VERY LOW ESR 0.1μF LOW ESR INPUT IDEAL DIODE Q2 TO BACKUP LOAD 0.1μF LOW ESR Q3 8.66k 1.21k INID DCIN 1nF 33Ω 0.5W 5% DCOUT NC CLN BATID CLP RTHA 1.13k CHGFET DCDIV DCHFET THA RTHB 54.9k VREF Q1B Q1A RSNS(FET) 0.05Ω 0.5W 1k 2k 1k RSNS(BAT) 0.1Ω 0.25W CSN VCHG 25.
