Datasheet

LTC4100
9
4100fc
For more information www.linear.com/LTC4100
block DiagraM
Figure 2
C7
0.0015µF
R5, 6.04k
+
–
+
–
+
+
1.28V
1.19V
WATCHDOG
DETECT
t
ON
OSCILLATOR
DCIN
PWM
LOGIC
S
R
Q
CA1
BUFFERED
I
TH
+
–
+
–
÷5
+
–
17mV
100mV
1.19V
1.2V
CLP
SMBus
INTERFACE
AND CONTROL
THERMISTER
INTERFACE
LIMIT
DECODER
I
CMP
I
REV
0V
V
SET
BAT
CSP
I
DC
I
LIM
V
LIM
I
TH
ACP
DCDIV
TO SMBUS
POWER SUPPLY
PGND
CLN
CLP
DCIN
INFET
CHGEN
SMBALERT
SDA
SCL
THA
THB
GND
CLP
TGATE
BGATE
SYSTEM
LOAD
EA
CL1
5.8V
11-BIT
V
DAC
10-BIT
I
DAC
3k
11.67µA
3k
9k
–
–
12
18
1
3
2
23
24
5
4
6
8
9
16
15
13
14
11
10
19
20
21
22
R4
100Ω
C4
0.01µF
C5, 0.1µF
V
BAT
V
BAT
CSP
CSP
Q2
Q3
Q1
R
CL
20µF
D1
L1
V
IN
V
IN
7
10µA
V
DD
R
SENSE
20µF
C8
0.068µF
R
VLIM
R
ILIM
17
V
DD
R1
C9
C1, 0.1µF
1.13k
TO HOST AND BATTERY
54.9k
10k
CA2
R10
R11
C6, 0.12µF
gm = 1m
Ω
gm = 1m
Ω
gm = 1.5m
Ω