Datasheet

LTC4100
20
4100fc
For more information www.linear.com/LTC4100
operaTion
The Current DAC Block
The current DAC is a delta-sigma modulator which controls
the effective value of an external resistor, R
SET
, used to
set the current limit of the charger. Figure 7 is a simplified
diagram of the DAC operation. The delta-sigma modulator
and switch convert the ChargingCurrent() value, received
via the SMBus, to a variable resistance equal to:
1.25R
SET
/[ChargingCurrent()/I
LIM[x]
] = R
IDC
Therefore, programmed current is equal to:
I
CHARGE
= (102.3mV/R
SENSE
) (ChargingCurrent()/
I
LIM[x]
), for ChargingCurrent() < I
LIM[x]
.
When a value less than 1/16th of the maximum current
allowed by I
LIM
is applied to the current DAC input, the
current DAC enters a different mode of operation called
LOWI. The current DAC output is pulse width modulated
with a high frequency clock having a duty cycle value of
1/8. Therefore,
the maximum output current provided by
the charger is I
MAX
/8. The delta-sigma output gates this
low duty cycle signal on and off. The delta-sigma shift
registers are then clocked at a slower rate, about 45ms/
bit, so that the charger has time to settle to the I
MAX
/8
value. The resulting average charging current is equal to
that
requested by the ChargingCurrent() value.
Note: The
LOWI mode can be disabled by setting the
NO_LOWI bit in the LTC0() function.
When wake-up is asserted to the current DAC block, the
delta-sigma is then fixed at a value equal to 80mA, inde
-
pendent of the I
LIM
setting.
Input FET
The input FET circuit performs two functions. It enables
the charger if the input voltage is higher than the CLP pin,
and provides an indication of this condition at both the
CHGEN pin and the PWR_FAIL bit in the ChargerStatus()
register. It also controls the gate of the input FET to keep
a low forward voltage drop when charging and prevents
reverse current flow through the input FET.
If the input voltage is less than V
CLP
, it must go at least
130mV higher than V
CLP
to activate the charger. The CHGEN
pin is forced low unless this condition is met. The gate
of the input FET is driven to a voltage sufficient to keep
a low forward voltage drop from drain to source. If the
voltage between DCIN and CLP drops to less than 25mV,
the input FET is turned off slowly. If the voltage
between
DCIN
and CLP is ever less than –25mV, then the input FET
is turned off quickly to prevent significant reverse current
from flowing in the input FET. In this condition the CHGEN
pin is driven low and the charger is disabled.
The AC Present Block (AC_PRESENT)
The DCDIV pin is used to determine AC presence. If the
DCDIV voltage is above the DCDIV comparator threshold
(V
ACP
), then the ACP output pin will be switched to V
DD
and
the AC_PRESENT bit in the ChargerStatus() function will be
set. If the DCDIV voltage is below the DCDIV comparator
threshold minus the DCDIV comparator hysteresis, then
the ACP output pin is switched to GND and the AC_PRES
-
ENT bit
in the ChargerStatus() function is cleared. The
ACP output pin is designed to drive 2mA continuously.
Figure 7. Current DAC Operation
I
PROG
(FROM CA1 AMP)
4100 F07
+
–
R
SET
V
REF
I
DC
CHARGING_CURRENT
VALUE
I
TH
∆-∑
MODULATOR
19
20
I
LIMIT
/8
AVERAGE CHARGER CURRENT
4100 F08
~40ms
0
Figure 8. Charging Current Waveform in Low Current Mode