Datasheet

LTC4099
21
4099fd
through I
LIM0
in the I
2
C port determine whether the sus-
pend LDO will limit input current to the low power setting
of 500µA or the high power setting of 2.5mA.
Interrupt Generation
The IRQ pin on
the LTC4099 is an open-drain output that
can be used to generate an interrupt based on one or more
of a multitude of maskable PowerPath/battery charger
change events. The interrupt mask register column in
Table 1 indicates the categories of events that can gener
-
ate an
interrupt. If a 1 is written to a given location in the
mask register, then any change in the status data of that
category will cause an interrupt to occur. For example, if
a 1 is written to bit 6 of the mask register, then an inter
-
rupt will
be generated when the WALL UVLO detects that
either power has become available at WALL, or that power
was available and is no longer available from WALL. If a
1 is written to bit 2 of the mask register, then an interrupt
will be triggered by any change in the status bits of the
battery charger, as given by Table 8. Likewise, a 1 at bit 3
will allow an interrupt due to any change in the thermistor
status bits of Table 7.
The
IRQ pin is cleared when the bus master acknowledges
receipt of status data from a read operation. If the master
does not acknowledge the status byte, the interrupt will
not be cleared and the
IRQ pin will not be released.
Upon generation of an interrupt, the current state of the
LTC4099 is recorded in the I
2
C port for retrieval (see
Output Data).
I
2
C Interface
The LTC4099 may communicate with a bus master using
the standard I
2
C 2-wire interface. The Timing Diagram
shows the relationship of the signals on the bus. The two
bus lines, SDA and SCL, must be HIGH when the bus is
not in use. External pull-up resistors or current sources,
such as the LTC1694 SMBus accelerator, are required
on these lines. The LTC4099 is both a slave receiver and
slave transmitter. The I
2
C control signals, SDA and SCL,
are scaled internally to the DV
CC
supply. DV
CC
should be
connected to the same power supply as the bus pull-up
resistors.
The I
2
C port has an undervoltage lockout on the DV
CC
pin.
When DV
CC
is below approximately 1V, the I
2
C serial port
is cleared, the LTC4099 is set to its default configuration
of all zeros and interrupts will be locked out.
Bus Speed
The I
2
C port is designed to be operated at speeds of up
to 400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I
2
C compliant master
device. It also contains input filters designed to suppress
glitches should the bus become corrupted.
START and STOP Conditions
A bus master signals the beginning of communications
by transmitting a START condition. A START condition is
generated by transitioning SDA from HIGH to LOW while
SCL is HIGH. The master may transmit either the slave
write or the slave read address. Once data is written to the
LTC4099, the master may transmit a STOP condition which
commands the LTC4099 to act upon its new command set.
A STOP condition is sent by the master by transitioning
SDA from LOW to HIGH while SCL is HIGH.
Byte Format
Each byte
sent to, or received from, the LTC4099 must
be eight bits long followed by an extra clock cycle for the
acknowledge bit. The data should be sent to the LTC4099
most significant bit (MSB) first.
Acknowledge
The acknowledge
signal is used for handshaking between
the master and the slave. When the LTC4099 is written
to (write address), it acknowledges its write address as
well as the subsequent two data bytes. When it is read
from (read address), the LTC4099 acknowledges its read
address only. The bus master should acknowledge receipt
of information from the LTC4099.
An acknowledge (active LOW) generated by the LTC4099
lets the master know that the latest byte of information was
received. The acknowledge related clock pulse is generated
by the master. The master releases the SDA line (HIGH)
during the acknowledge clock cycle. The LTC4099 pulls
operaTion