Datasheet

LTC4089-3
21
40893f
For more information www.linear.com/4089-3
Power Dissipation and High Temperature
Considerations
The die temperature of the LTC4089-3 must be lower than
the maximum rating of 110°C. This is generally not a con-
cern unless the ambient temperature is above 85°C. The
total power dissipated inside the LTC4089-3 depends on
many factors, including input voltage (IN or HVIN), battery
voltage, programmed charge current, programmed input
current limit, and load current.
In general, if the LTC4089-3 is being powered from IN the
power dissipation can be calculated as follows:
P
D
= (V
IN
– V
BAT
) • I
BAT
+ (V
IN
–V
OUT
) • I
OUT
where P
D
is the power dissipated, I
BAT
is the battery
charge current, and I
OUT
is the application load current.
For a typical application, an example of this calculation
would be:
P
D
= (5V – 3.7V) • 0.4A + (5V – 4.75V) • 0.1A = 545mW
This example assumes V
IN
= 5V, V
OUT
= 4.75V, V
BAT
= 3.7V,
I
BAT
= 400mA, and I
OUT
= 100mA resulting in slightly more
than 0.5W total dissipation.
If the LTC4089-3 is being powered from HVIN, the power
dissipation can be estimated by calculating the regulator
power loss from an efficiency measurement, and subtract-
ing the catch diode loss.
P
D
= (1− η) • (V
HVOUT
• (I
BAT
+ I
OUT
)) − V
D
•
1−
V
HVOUT
V
HVIN






• (I
BAT
+ I
OUT
) + 0.3V • I
BAT
where is the efficiency of the high voltage regulator and
V
D
is the forward voltage of the catch diode at I = I
BAT
+ I
OUT
. The first term corresponds to the power lost in
converting V
HVIN
to V
HVOUT
, the second term subtracts
the catch diode loss, and the third term is the power
dissipated in the battery charger. For a typical application,
an example of this calculation would be:
P
D
= (1− 0.87) • 4V • (0.7A + 0.3A)
[ ]
− 0.4V •
1−
4V
12V






• (0.7A + 0.3A) + 0.3V • 0.7A
= 463mW
This example assumes 87% efficiency, V
HVIN
= 12V, V
BAT
=
3.7V (V
HVOUT
is about 4V), I
BAT
= 700mA, I
OUT
= 300mA
resulting in less than 0.5W total dissipation.
To prevent power dissipation of this magnitude from
causing high die temperature, it is important to solder the
exposed backside of the package to a ground plane. This
ground should be tied to other copper layers below with
thermal vias; these layers will spread the heat dissipated by
the LTC4089-3v. Additional vias should be placed near the
catch diodes. Adding more copper to the top and bottom
layers, and tying this copper to the internal planes with
vias, can reduce thermal resistance further. With these
steps, the thermal resistance from die (i.e., junction) to
ambient can be reduced to
JA
= 40°C/W.
The power dissipation in the other power compo-
nents—catch diodes, MOSFETs, boost diodes and induc-
tors—causes additional copper heating and can further
increase the “ambient” temperature of the IC.
Board Layout Considerations
As discussed in the previous section, it is critical that
the exposed metal pad on the backside of the LTC4089-3
package be soldered to the PC board ground. Further-
more, proper operation and minimum EMI requires a
careful printed circuit board (PCB) layout. Note that large,
switched currents flow in the power switch (between the
HVIN and SW pins), the catch diode and the HVIN input
capacitor. These components, along with the inductor and
output capacitor, should be placed on the same side of
the circuit board, and their connections should be made
on that layer. Place a local, unbroken ground plane below
these components. The loop formed by these components
should be as small as possible. Additionally, the SW and
BOOST nodes should be kept as small as possible. Figure 8
shows the recommended component placement with trace
and via locations.
APPLICATIONS INFORMATION