Datasheet

LTC4071
3
4071fc
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC4071 is tested under pulsed load conditions such that
T
J
≈ T
A
. The LTC4071E is guaranteed to meet performance specifications
for junction temperatures from 0°C to 85°C. Specifications over the
The l denotes the specifications which apply over the full operating
junction temperature range. Conditions are V
NTC
= V
ADJ
= V
CC
, V
LBSEL
= GND, T
J
= 25°C unless otherwise specified. Current into a pin
is positive and current out of a pin is negative. All voltages are referenced to GND unless otherwise noted. (Note 2)
–40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTC4071I is guaranteed over the full –40°C to 125°C operating
junction temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operation
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Low Battery Disconnect
I
LEAK
Battery Disconnect Leakage
Current
V
CC
< V
BAT
= 2.65V
l
0.01
0.01
25 nA
nA
R
DSON
Resistance of V
CC
– BAT Switch I
BAT
= –1mA, V
HBO
High 4 6 Ω
V
LBD
Low Battery Disconnect V
BAT
Falling, I
BAT
= –1mA, LBSEL = V
CC
, 0°C < Temp < 125°C 2.60 2.70 2.79 V
V
BAT
Falling, I
BAT
= –1mA, LBSEL = V
CC
l
2.52 2.70 2.79 V
V
BAT
Falling, I
BAT
= –1mA, LBSEL = GND, 0°C < Temp < 125°C 3.05 3.20 3.28 V
V
BAT
Falling, I
BAT
= –1mA, LBSEL = GND
l
2.95 3.20 3.28 V
V
LBC_BAT
Low Battery Connect V
BAT
Rising, I
BAT
= –1mA, LBSEL = V
CC
2.97 V
V
BAT
Rising, I
BAT
= –1mA, LBSEL = GND 3.53 V
V
LBC_VCC
Low Battery Connect V
CC
Rising, LBSEL = V
CC
V
CC
Rising, LBSEL = GND
3.6
4.19
V
V
High Battery Status
V
HBTH
HBO Threshold (V
FLOAT
– V
CC
) V
CC
Rising
l
15 40 75 mV
V
HBHY
Hysteresis 100 mV
Status Output: HBO
V
OL
CMOS Output Low I
SINK
= 1mA, V
CC
= 3.7V 0.5 V
V
OH
CMOS Output High I
SOURCE
= –0.5mA, I
CC
= 1.5mA V
CC
– 0.6 V
Selection Inputs: ADJ, LBSEL
V
ADJ_IL
ADJ V
IL
Input Logic Low Level
l
0.3 V
V
ADJ_IH
ADJ V
IH
Input Logic High Level
l
V
CC
– 0.3 V
I
ADJ(Z)
Allowable ADJ Leakage Current
in Floating State
l
±3 µA
V
LBSEL_IL
LBSEL V
IL
Input Logic Low Level
l
250 mV
V
LBSEL_IH
LBSEL V
IH
Input Logic High Level
l
1.4 V
I
LBSEL
LBSEL Leakage Current 0 ≤ LBSEL ≤ V
CC
l
–5 0 5 nA
NTC
I
NTC
NTC Leakage Current 0V ≤ NTC ≤ V
CC
l
–5 0 5 nA
I
NTCBIAS
Average NTCBIAS Sink Current Pulsed Duty Cycle < 0.002% 30 50 pA
NTC
TH1
NTC Comparator Falling
Thresholds
V
NTC
as Percentage of V
NTCBIAS
Amplitude 35.5 36.5 38 %
NTC
TH2
28.0 29.0 30.5 %
NTC
TH3
21.8 22.8 23.8 %
NTC
TH4
16.8 17.8 18.8 %
NTC
HY
Hysteresis 30 mV
∆V
FLOAT(NTC)
Delta Float Voltage per NTC
Comparator Step
NTC Falling Below One of the NTC
TH
Thresholds
ADJ = 0V
ADJ = Floating
ADJ = V
CC
–57
–82
–107
–50
–75
–100
–43
–68
–93
mV
mV
mV