Datasheet

11
LTC4068-4.2/LTC4068X-4.2
406842fa
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
U
PACKAGE DESCRIPTIO
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
4. EXPOSED PAD SHALL BE SOLDER PLATED
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
2.38 ±0.10
(2 SIDES)
14
85
PIN 1
TOP MARK
0.200 REF
0.00 – 0.05
(DD8) DFN 0203
0.28 ± 0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.675 ±0.05
3.5 ±0.05
PACKAGE
OUTLINE
0.28 ± 0.05
0.50 BSC
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
APPLICATIO S I FOR ATIO
WUUU
V
IN
V
CC
LTC4068
DRAIN-BULK
DIODE OF FET
405842 F04
Figure 4. Low Loss Input Reverse Polarity Protection
Reverse Polarity Input Voltage Protection
In some applications, protection from reverse polarity
voltage on V
CC
is desired. If the supply voltage is high
enough, a series blocking diode can be used. In other
cases, where the voltage drop must be kept low, a P-channel
MOSFET can be used (as shown in Figure 4).