Datasheet

LTC4062
11
4062fb
Smart Pulsing Error Feature
LTC4062 has a pulsing state at the CHRG pull-down pin of
6Hz (50% duty cycle) due to defective battery detection
(see Trickle-Charge and Defective Battery Detection sec-
tion).
Low Power Comparator (IN
+
; OUT)
The low power, low offset comparator is designed with an
internal 1V reference connected to the negative input. This
reference is generated by a precise bandgap circuit. The
–
+
1V
2
LTC4062
4062 F01
IN
+
4
OUT
Figure 1. Low Power Comparator Circuit
comparator output drives a pull down NMOS transistor
able to sink up to 10mA. Voltages lower than 1V at the IN
+
pin set the OUT pin to a high impedance state.
Voltages higher than 1V plus a built-in 50mV hysteresis at
the IN
+
pin set the OUT pin to a low impedance state. The
comparator is operational even when V
CC
is not applied
provided the BAT pin voltage is greater than 2.5V. When
the voltage at the BAT pin drops below 2.5V, the compara-
tor shuts down and the current at the BAT pin is reduced
to <1µA.
OPERATIO
U