Datasheet

LTC4011
23
4011fb
capacitors. Vias should not be used to make these
connections.
2. Place
the LTC4011 close to the switching FET gate
terminals, keeping the connecting traces short to
produce clean drive signals. This rule also applies to IC
supply and ground pins that connect to the switching
FET source pins. The IC can be placed on the opposite
side of the PCB from the switching FETs.
3. Place the inductor input as close as possible to the
drain of the switching FETs. Minimize the surface area
of the switch node. Make the trace width the minimum
needed to support the programmed charge current.
Use no copper fills or pours. Avoid running the con
-
nection on
multiple copper layers in parallel. Minimize
capacitance from the switch node to any other trace
or plane.
4. Place the charge current sense resistor immediately
adjacent to the inductor output, and orient it such that
current sense traces to the LTC4011 are short. These
feedback traces need to be run together as a single pair
with the smallest spacing possible on any given layer
on which they are routed. Locate any filter component
on these traces next to the LTC4011, and not at the
sense resistor location.
5. Place output capacitors adjacent to the sense resisitor
output and ground.
6. Output capacitor ground connections must feed into
the same copper that connects to the input capacitor
ground before tying back into system ground.
7. Connection of switching ground to system ground,
or any internal ground plane should be single-point.
If the system has an internal system ground plane, a
good way to do this is to cluster vias into a single star
point to make the connection.
8. Route analog ground as a trace tied back to the LTC4011
GND pin before connecting to any other ground. Avoid
using the system ground plane. A useful CAD technique
is to make analog ground a separate ground net and
use a 0Ω resistor to connect analog ground to system
ground.
9. A good rule of thumb for via count in a given high
current path is to use 0.5A per via. Be consistent when
applying this rule.
10. If possible, place all the parts listed above on the same
PCB layer.
11. Copper fills or pours are good for all power connec
-
tions except as noted above in Rule 3. Copper planes
on multiple layers can also be used in parallel. This
helps with thermal management and lowers trace in
-
ductance, which further improves EMI performance.
12. For best current programming accuracy, provide a
Kelvin connection from R
SENSE
to SENSE and BAT.
See Figure 14 for an example.
13. It is important to minimize parasitic capacitance on the
TIMER, SENSE and BAT pins. The traces connecting
these pins to their respective resistors should be as
short as possible.
Figure 13. High Speed Switching Path
4011 F13
V
BAT
L1
V
IN
HIGH
FREQUENCY
CIRCULATING
PATH
BAT
SWITCH NODE
C
IN
SWITCHING GROUND
C
OUT
D1
Figure 14. Kelvin Sensing of Charge Current
SENSE
4011 F14
DIRECTION OF CHARGING CURRENT
R
SENSE
BAT
applicaTions inForMaTion