Datasheet

17
LTC4011
4011fa
greatly increase internal power dissipation at elevated V
CC
voltages. A minimum ceramic bypass capacitor of 0.1µF is
recommended.
Calculating Average Power Dissipation
The user should ensure that the maximum rated IC junc-
tion temperature is not exceeded under all operating
conditions. The thermal resistance of the LTC4011 pack-
age (θ
JA
) is 38°C/W, provided the exposed metal pad is
properly soldered to the PCB. The actual thermal resis-
tance in the application will depend on the amount of PCB
copper to which the package is soldered. Feedthrough vias
directly below the package that connect to inner copper
layers are helpful in lowering thermal resistance. The
following formula may be used to estimate the maximum
average power dissipation P
D
(in watts) of the LTC4011
under normal operating conditions.
where:
I
DD
= Average external INTV
DD
load current, if any
I
VRT
= Load current drawn by the external thermistor
network from V
RT
, if any
Q
TGATE
= Gate charge of external P-channel MOSFET
in coulombs
Q
BGATE
= Gate charge of external N-channel MOSFET
(if used) in coulombs
V
LED
= Maximum external LED forward voltage
R
LED
= External LED current-limiting resistor used in
the application
n = Number of LEDs driven by the LTC4011
Sample Applications
Figures 6 through 9 detail sample charger applications of
various complexities. Combined with the Typical Applica-
tion on the first page of this data sheet, these Figures
demonstrate some of the proper configurations of the
LTC4011. MOSFET body diodes are shown in these fig-
ures strictly for reference only.
Figure 6 shows a minimum application, which might be
encountered in low cost NiCd fast charge applications.
FET-based PowerPath control allows for maximum input
voltage range from the DC adapter. The LTC4011 uses
–∆V to terminate the fast charge state, as no external
temperature information is available. Nonsynchronous
PWM switching is employed to reduce external compo-
nent cost. A single LED indicates charging status.
A 3A NiMH application of medium complexity is shown
in Figure 7. PowerPath control that is completely FET-
based allows for both minimum input voltage overhead
and minimum switchover loss when operating from the
battery.
P-channel MOSFET Q4 functions as a switch to connect
the battery to the system load whenever the DC input
adapter is removed. If the maximum battery voltage is less
than the maximum rated V
GS
of Q4, diode D1 and resistor
R5 are not required. Otherwise choose the Zener voltage
of D1 to be less than the maximum rated V
GS
of Q4. R5
provides a bias current of (V
BAT
– V
ZENER
)/(R5 + 20k) for
D1 when the input adapter is removed. Choose R5 to make
this current, which is drawn from the battery, just large
enough to develop the desired V
GS
across D1.
Precharge, fast charge and top-off states are indicated by
external LEDs. The V
TEMP
thermistor network allows the
LTC4011 to accurately terminate fast charge under a
variety of applied charge rates. Use of a synchronous
PWM topology improves efficiency and lowers power
dissipation.
A full-featured 2A LTC4011 application is shown in Fig-
ure 8. FET-based PowerPath allows for maximum input
voltage range from the DC adapter. The inherent voltage
ratings of the V
CELL
, V
CDIV
, SENSE and BAT pins allow
charging of one to sixteen series nickel cells in this
application, governed only by the V
CC
overhead limits
previously discussed. The application includes all average
cell voltage and battery temperature sensing circuitry
required for the LTC4011 to utilize its full range of charge
qualification, safety monitoring and fast charge termina-
tion features. A green LED indicates valid DC input voltage
APPLICATIO S I FOR ATIO
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