Datasheet

LTC4010
12
4010fb
Figure 2. LTC4010 PWM Control Loop
10
+
CC
EA
I
TH
I
PROG
R3
Q
PWM CLOCK
S
R
R4
R1
BAT
9
SENSE
R
SENSE
12
BGATE
14
TGATE
LTC4010
V
CC
R2
4010 F02
operaTion
(Refer to Figure 1)
Status Outputs
The LTC4010 open-drain status outputs provide valuable
information about the IC’s operating state and can be
used for a variety of purposes in applications. Table 1
summarizes the state of the three status outputs and the
V
CDIV
pin as a function of LTC4010 operation. The status
outputs can directly drive current-limited LEDs terminated
to the DC input. The V
CDIV
column in Table 1 is strictly
informational. V
CDIV
should only be used to terminate the
V
CELL
resistor divider, as previously discussed.
Table 1. LTC4010 Status Pins
READY FAULT CHRG V
CDIV
CHARGER STATE
Off Off Off Off Off
On Off Off On Ready to Charge
(V
TEMP
Held Low)
or Automatic Recharge
On Off On On Precharge, Fast or Top Off
Charge (May be Paused)
On On On or Off On Temperature Limits
Exceeded
Off On Off On Fault State (Latched)
PWM Current Source Controller
An integral part of the LTC4010 is the PWM current source
controller. The charger uses a synchronous step-down
architecture to produce high efficiency and limited thermal
dissipation. The nominal operating frequency of 550kHz
allows use of a smaller external inductor. The TGATE and
BGATE outputs have internally clamped voltage swings.
They source peak currents tailored to smaller surface-
mount power FETs likely to appear in applications providing
an average charge current of 3A or less. During the various
charging states, the LTC4010 uses the PWM controller to
regulate an average voltage between SENSE and BAT that
ranges from 10mV to 100mV.
A conceptual diagram of the LTC4010 PWM control loop
is shown in Figure 2.
The voltage across the external current programming
resistor R
SENSE
is averaged by integrating error amplifier
EA. An internal programming current is also pulled from
input resistor R1. The I
PROG
R1 product establishes the
desired average voltage drop across R
SENSE
, and hence,