Datasheet

5
LTC4001
4001f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Soft-Start (PWM Mode)
IDET Threshold vs R
IDET
for
R
PROG
= 549
UU
U
PI FU CTIO S
BAT (Pin 1): Battery Charger Output Terminal. Connect a
10µF ceramic chip capacitor between BAT and PGND to
keep the ripple voltage small.
SENSE (Pin 2): Internal Sense Resistor. Connect to exter-
nal inductor.
PGND (Pin 3): Power Ground.
GNDSENS (Pin 4): Ground Sense. Connect this pin to the
negative battery terminal. GNDSENS provides a Kelvin
connection for PGND and must be connected to PGND
schematically.
SW (Pin 5): Switch Node Connection. This pin connects to
the drains of the internal main and synchronous power
MOSFET switches. Connect to external inductor.
EN (Pin 6): Enable Input Pin. Pulling the EN pin high places
the LTC4001 into a low power state where the BAT drain
current drops to less than 3µA and the supply current is
reduced to less than 50µA. For normal operation, pull the
pin low.
CHRG (Pin 7): Open-Drain Charge Status Output. When
the battery is being charged, CHRG is pulled low by an
internal N-channel MOSFET. When the charge current
drops below the IDET threshold (set by the R
IDET
program-
ming resistor) for more than 5milliseconds, the N-channel
MOSFET turns off and a 30µA current source is connected
from CHRG to ground. (This signal is latched and is reset
by initiating a new charge cycle.) When the timer runs out
or the input supply is removed, the current source will be
disconnected and the CHRG pin is forced to a high imped-
ance state. A temperature fault causes this pin to blink.
PV
IN
(Pin 8): Positive Supply Voltage Input. This pin
connects to the power devices inside the chip. V
IN
ranges
from 4V to 5.5V for normal operation. Operation down to
the undervoltage lockout threshold is allowed with current
limited wall adapters. Decouple with a 10µF or larger
surface mounted ceramic capacitor.
V
INSENSE
(Pin 9): Positive Supply Sense Input. This pin
connects to the inputs of all input comparators (UVL, V
IN
to V
BAT
). It also supplies power to the controller portion of
this chip. When the BATSENS pin rises to within 30mV of
V
INSENSE
, the LTC4001 enters sleep mode, dropping I
IN
to
50µA. Tie this pin directly to the terminal of the PV
IN
decoupling capacitor.
CHRG Pin Temperature Fault
Behavior (Detail)
0
INPUT
CURRENT (I
IN
)
0.5A/DIV
INDUCTOR
CURRENT (I
L
)
0.5A/DIV
SOFT-START
VOLTAGE (V
SS
)
1V/DIV
EN PIN (V
EN
)
5V/DIV
0
0
0
2ms/DIVV
BAT
= 3.5V
V
IN
= 5V
4001 G09
R
IDET
()
300
IDET (mA)
200
250
300
1100
4001 G10
150
100
0
500
700
900
400 1200
600
800
1000
50
400
350
CHRG
1V/DIV
TIME (20µs/DIV)
4001 G11