Datasheet

LTC3891
9
3891fa
PIN FUNCTIONS
PLLIN/MODE (Pin 1/Pin 3): External Synchronization
Input to Phase Detector and Forced Continuous Mode
Input. When an external clock is applied to this pin, the
phase-locked loop will force the rising TG signal to be
synchronized with the rising edge of the external clock,
and the regulator operates in forced continuous mode.
When not synchronizing to an external clock, this input
determines how the LTC3891 operates at light loads. Pull-
ing this pin to ground selects Burst Mode operation. An
internal 100k resistor to ground also invokes Burst Mode
operation when the pin is floated. Tying this pin to INTV
CC
forces continuous inductor current operation. Tying this
pin to a voltage greater than 1.2V and less than INTV
CC
–1.3V selects pulse-skipping operation.
SGND (Pins 2, 3, Exposed Pad Pin 21/Pins 4, 5,
Exposed Pad Pin 21): Small-signal ground, must be routed
separately from high current grounds to the common
(–) terminals of the C
IN
capacitor. Pins 2, 3/4, 5, must
both be electrically connected to small signal ground for
proper operation.The exposed pad must be soldered to
PCB ground for rated thermal performance.
RUN (Pin 4/Pin 6): Digital Run Control Input. Forcing this
pin below 1.16V shuts down the controller. Forcing this
pin below 0.7V shuts down the entire LTC3891, reducing
quiescent current to approximately 14µA.
SENSE
–
(Pin 5/Pin 7): The (–) Input to the Differential
Current Comparator. When greater than INTV
CC
– 0.5V, the
SENSE
–
pin supplies power to the current comparator.
SENSE
+
(Pin 6/Pin 8): The (+) input to the differential
current comparator is normally connected to DCR sensing
network or current sensing resistor. The ITH pin voltage and
controlled offsets between the SENSE
–
and SENSE
+
pins in
conjunction with R
SENSE
set the current trip threshold.
V
FB
(Pin 7/Pin 9): Receives the remotely sensed feed-
back voltage from an external resistive divider across
the output.
ITH (Pin 8/Pin 10): Error Amplifier Outputs and Switching
Regulator Compensation Point. The current comparator
trip point increases with this control voltage.
PGOOD (Pin 9/Pin 11): Open-Drain Logic Output. PGOOD
is pulled to ground when the voltage on the V
FB
pin is not
within 10% of its set point.
TG (Pin 10/Pin 12): High Current Gate Drives for Top
N-channel MOSFET. This is the output of floating driver
with a voltage swing equal to INTV
CC
superimposed on
the switch node voltage SW.
SW (Pin 11/ Pin 13): Switch Node Connection to Induc-
tor.
BOOST (Pin 12/Pin 14): Bootstrapped Supply to the Top-
side Floating Driver. A capacitor is connected between the
BOOST and SW pin and a Schottky diode is tied between
the BOOST and INTV
CC
pins. Voltage swing at the BOOST
pin is from INTV
CC
to (V
IN
+ INTV
CC
).
BG (Pin 13/Pin 15): High Current Gate Drive for Bottom
(Synchronous) N-channel MOSFET. Voltage swing at this
pin is from ground to INTV
CC
.
INTV
CC
(Pin 14/Pin 16): Output of the Internal Linear
Low Dropout Regulator. The driver and control circuits
are powered from this voltage source. Must be decoupled
to PGND with a minimum of 2.2µF ceramic or other low
ESR capacitor. Do not use the INTV
CC
pin for any other
purpose.
EXTV
CC
(Pin 15/Pin 17): External Power Input to an
Internal LDO Connected to INTV
CC
. This LDO supplies
INTV
CC
power, bypassing the internal LDO powered from
V
IN
whenever EXTV
CC
is higher than 4.7V. See EXTV
CC
Connection in the Applications Information section. Do
not float or exceed 14V on this pin.
PGND (Pin 16/Pin 18): Driver Power Ground. Connects to
the source of bottom (synchronous) N-channel MOSFET
and the (–) terminal of C
IN
.
V
IN
(Pin 17/Pin 19): Main Supply Pin. A bypass capacitor
should be tied between this pin and the SGND pins.
I
LIM
(Pin 18/Pin 20): Current Comparator Sense Voltage
Range Inputs. Tying this pin to SGND, FLOAT or INTV
CC
sets the maximum current sense threshold to one of three
different levels for the comparator.
(QFN/eTSSOP)