Datasheet

LTC3891
22
3891fa
Phase-Locked Loop and Frequency Synchronization
The LTC3891 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass filter,
and a voltage-controlled oscillator (VCO). This allows the
turn-on of the top MOSFET to be locked to the rising edge
of an external clock signal applied to the PLLIN/MODE pin.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, f
OSC
, then current is sourced
continuously from the phase detector output, pulling up
the VCO input. When the external clock frequency is less
than f
OSC
, current is sunk continuously, pulling down the
VCO input.
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
CLP, holds the voltage at the VCO input.
Note that the LTC3891 can only be synchronized to an
external clock whose frequency is within range of the
LTC3891’s internal VCO, which is nominally 55kHz to
900kHz.
This is guaranteed to be between 75kHz and 750kHz. Typi-
cally, the external clock (on the PLLIN/MODE pin) input high
threshold is 1.6V, while the input low threshold is 1.1V.
Rapid phase locking can be achieved by using the FREQ pin
to set a free-running frequency near the desired synchro-
nization frequency. The VCO’s input voltage is prebiased
at a frequency corresponding to the frequency set by the
FREQ pin. Once prebiased, the PLL only needs to adjust
APPLICATIONS INFORMATION
the frequency slightly to achieve phase lock and synchro-
nization. Although it is not required that the free-running
frequency be near external clock frequency, doing so will
prevent the operating frequency from passing through a
large range of frequencies as the PLL locks.
Table 2 summarizes the different states in which the FREQ
pin can be used.
Table 2
FREQ PIN PLLIN/MODE PIN FREQUENCY
0V DC Voltage 350kHz
INTV
CC
DC Voltage 535kHz
Resistor DC Voltage 50kHz to 900kHz
Any of the Above External Clock Phase Locked to
External Clock
Minimum On-Time Considerations
Minimum on-time, t
ON(MIN)
, is the smallest time duration
that the LTC3891 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
FREQ PIN RESISTOR (kΩ)
15
FREQUENCY (kHz)
600
800
1000
35 45 5525
3891 F09
400
200
500
700
900
300
100
0
65 75 85 95 105 115
125
Figure 9. Relationship Between Oscillator Frequency and
Resistor Value at the FREQ Pin