Datasheet

LTC3890-1
26
38901fb
APPLICATIONS INFORMATION
A 4.7µH inductor will produce 29% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 5.73A. Increasing the ripple
current will also help ensure that the minimum on-time
of 95ns is not violated. The minimum on-time occurs at
maximum V
IN
:
t
ON(MIN)
=
V
OUT
V
IN(MAX)
f
( )
=
3.3V
22V 350kHz
( )
= 429ns
The equivalent R
SENSE
resistor value can be calculated by
using the minimum value for the maximum current sense
threshold (43mV):
R
SENSE
≤
64mV
5.73A
≈ 0.01Ω
Choosing 1% resistors: R
A
= 25k and R
B
= 78.7k yields
an output voltage of 3.32V.
The power dissipation on the topside MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: R
DS(ON)
= 0.035Ω/0.022Ω, C
MILLER
= 215pF. At
maximum input voltage with T(estimated) = 50°C:
P
MAIN
=
3.3V
22V
5A
( )
2
1+ 0.005
( )
50°C – 25°C
( )




0.035Ω
( )
+ 22V
( )
2
5A
2
2.5Ω
( )
215pF
( )
•
1
5V – 2.3V
+
1
2.3V






350kHz
( )
= 331mW
A short-circuit to ground will result in a folded back cur-
rent of:
I
SC
=
34mV
0.01Ω
–
1
2
95ns 22V
( )
4.7µH






= 3.18A
with a typical value of R
DS(ON)
and δ = (0.005/°C)(25°C)
= 0.125. The resulting power dissipated in the bottom
MOSFET is:
P
SYNC
= 3.18A
( )
2
1.125
( )
0.022Ω
( )
=
250mW
which is less than under full-load conditions.
C
IN
is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. C
OUT
is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
V
ORIPPLE
= R
ESR
(∆I
L
) = 0.02Ω(1.45A) = 29mV
P-P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 11. Figure 12 illustrates the current
waveforms present in the various branches of the 2-phase
synchronous regulators operating in the continuous mode.
Check the following in your layout:
1. Are the top N-channel MOSFETs MTOP1 and MTOP2
located within 1cm of each other with a common drain
connection at C
IN
? Do not attempt to split the input
decoupling for the two channels as it can cause a large
resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of C
INTVCC
must return to the combined C
OUT
(–) ter-
minals. The path formed by the top N-channel MOSFET,
Schottky diode and the C
IN
capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
3. Do the LTC3890-1 V
FB
pins’ resistive dividers connect to
the (+) terminals of C
OUT
? The resistive divider must be
connected between the (+) terminal of C
OUT
and signal
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).