Datasheet

LTC3883/LTC3883-1
45
3883fa
For more information www.linear.com/LTC3883
APPLICATIONS INFORMATION
voltage exceeds the R
DS(ON)
test voltage for the MOSFETs
which is typically 4.5V for logic level devices. The UVLO
on INTV
CC
(EXTV
CC
) is set to approximately 4V. Both the
LTC3883 and LTC3883-1 are valid for this configuration.
TOPSIDE MOSFET DRIVER SUPPLY (C
B
, D
B
)
External bootstrap capacitors C
B
connected to the BOOST
pin supplies the gate drive voltages for the topside MOS-
FETs. Capacitor
C
B
in the Block Diagram is charged though
external diode D
B
from INTV
CC
when the SW pin is low.
When one of the topside MOSFETs is to be turned on,
the driver places the C
B
voltage across the gate source
of the desired MOSFET. This enhances the MOSFET and
turns on the topside switch. The switch node voltage, SW,
rises to V
IN
and the BOOST pin follows. With the topside
MOSFET on, the boost voltage is above the input supply:
V
BOOST
= V
IN
+ V
INTVCC
. The value of the boost capacitor
C
B
needs to be 100 times that of the total input capacitance
of the topside MOSFET(s). The reverse breakdown of the
external Schottky diode must be greater than V
IN(MAX)
.
When adjusting the gate drive level, the final arbiter is the
total
input current for the regulator. If a change is made
and the input current decreases, then the efficiency has
improved. If there is no change in input current, then there
is no change in efficiency.
PWM jitter has been observed in some designs operating
at higher V
IN
/V
OUT
ratios. This jitter does not substantially
affect the circuit accuracy. Referring to Figure 24, PWM
jitter can be removed by inserting a series resistor with a
value of 1Ω to 5Ω between the cathode of the diode and
the BOOST pin. A resistor case size of 0603 or larger is
recommended to reduce ESL and achieve the best results.
UNDERVOLTAGE LOCKOUT
The LTC3883 is initialized by an internal threshold-based
UVLO where V
IN
must be approximately 4V and INTV
CC
/
EXTV
CC
, V
DD33
, V
DD25
must be within approximately 20%
of the regulated values. In addition, V
DD33
must be within
approximately 7% of the targeted value before the RUN
pin is released. After the part has initialized, an additional
comparator monitors V
IN
. The VIN_ON threshold must be
exceeded before the power sequencing can begin. When
V
IN
drops below the VIN_OFF threshold, the SHARE_CLK
pin will be pulled low and V
IN
must increase above the
VIN_ON threshold before the controller will restart.
The normal start-up sequence will be allowed after the
VIN_ON threshold is crossed. If GPIO is held low when
V
IN
is applied, ALERT will be asserted low even if the part
is programmed to not assert ALERT when GPIO is held
low. If I
2
C communication occurs before the LTC3883 is
out of reset and only a portion of the command is seen by
the part, this can be interpreted as a CML fault. If a CML
fault is detected, ALERT is asserted low.
It is possible to program the contents of the NVM in the
application if the V
DD33
supply is externally driven. This will
activate the digital portion of the LTC3883 without engaging
the high voltage sections. PMBus communications are valid
in this supply configuration. If V
IN
has not been applied to
the LTC3883, bit 3 (NVM Not Initialized)in MFR_COMMON
will be asserted low. If this condition is detected, the part
will only respond to addresses 5A and 5B. To initialize
the part issue the following set of commands: global
address 0x5B command
0xBD data 0
x2B followed by
global address 5B command 0xBD and data 0xC4. The
part will now respond to the correct address. Configure
the part as desired then issue a STORE_USER_ALL. When
V
IN
is applied a MFR_RESET command must be issued to
allow the PWM to be enabled and valid ADC conversions
to be read.
C
IN
AND C
OUT
SELECTION
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (V
OUT
)/(V
IN
). To prevent
large voltage transients, a low ESR capacitor sized for the
Figure 24. Boost Circuit to Minimize PWM Jitter
V
IN
TGATE
LTC3883/
LTC3883-1
SW
D
B
INTV
CC
/EXTV
CC
BOOST
C
B
0.2µF
1Ω TO 5Ω
V
IN
C
INTVCC
10µF
3883 F24
BGATE
PGND