Datasheet

LTC3883/LTC3883-1
14
3883fa
For more information www.linear.com/LTC3883
BLOCK DIAGRAM
16-BIT
ADC
PWM1
+
–
–
+
–
–
+
+
+
+
–
–
PWM0
–
+
–
+
–
+
8:1
MUX
TMUX
2µA
I
LIM
DAC
(3 BITS)
OV
8-BIT
OV
DAC
8-BIT
UV
DAC
12-BIT
SET POINT
DAC
UVEA
+
0.56V
1.22V
BURST
I
TH
R
C
C
C1
GND
30µA
–
+
–
+
AO
R
R
9R
2R
GND
PWM
CLOCK
V
OUT_CFG
R
V
SENSE
+
TSNS
V
SENSE
–
R
SWITCH
LOGIC
AND
ANTI-
SHOOT-
THROUGH
OV
RUN
SS
UVLO
REV
UV
ON
FCNT
31
30
32
15
V
TRIM_CFG
17
FREQ_CFG
14
ASEL
3883 F01
13
9
11
PGND
C
INTVCC
25
BG
D
B
M1
INTV
CC
/EXTV
CC
V
DD33
26
I
SENSE
–
4
I
SENSE
+
3
SW
22
TG
C
B
23
BOOST
24
V
DD33
21
V
IN
C
VIN
28
1
INTV
CC
/EXTV
CC
(LTC3883-1)
27
M2
C
OUT
V
OUT
+
3.3V
SUBREG
2.5V
SUBREG
5V REG
–
+
–
+
–
+
–
+
1
71.1k
ACTIVE
CLAMP
UVLOINTV
CC
SLOPE
COMPENSATION
SLAVE
V
DD33
MISO
MOSICLK
MASTER
RAM
SYNC
RUN
10
PGOOD
GPIO
EEPROM
MAIN
CONTROL
PROGRAM
ROM
V
DD33
COMPARE
I
LIM
RANGE SELECT
HI: 1:1
LO: 1:1.5
3k
38R
I
IN
R
I
CMP
I
REV
29
33
1Ω
+
–
+
–
S
REF
V
STBY
GND
Q
PWM_CLOCK
V
IN_SNS
R
IINSNS R
VIN
V
IN
C
IN
2
I
IN_SNS
R
8-BIT
V
IN_ON
THRESHOLD DAC
PHASE DET
V
CO
PHASE SELECTOR
CLOCK DIVIDER
SINC
3
UVLO
OSC
(32MHz)
CONFIG
DETECT
CHANNEL
TIMING
MANAGEMENT
8
7
6
19
WP
SHARE_CLK
SCL
SDA
ALERT
PMBus
INTERFACE
(400kHz
COMPATIBLE)
20
SYNC
GND
M2
GND
V
DD33
5
V
DD25
18
V
DD25
LTC3883
ONLY
19.5R
R
+
–
+
Figure 1. Block Diagram