Datasheet

LTC3880/LTC3880-1
57
3880fc
For more information www.linear.com/LTC3880
APPLICATIONS INFORMATION
path voltage pickup between these components and the
SGND pin of the IC.
DESIGN EXAMPLE
As a design example for a two channel medium current
regulator, assume V
IN
= 12V nominal, V
IN
= 20V maximum,
V
OUT0
= 3.3V, V
OUT1
= 1.8V, I
MAX0,1
= 15A and f = 500kHz
(see Figure 27).
The regulated output is established by the VOUT_
COMMAND stored in NVM or placing the following resis-
tor divider between VDD25 the RCONFIG pin and SGND:
1.
VOUT0_CFG, R
TOP
= 10k, R
BOTTOM
= 15.8k
2. VTRIM0_CFG, Open
3. VOUT1_CFG, R
TOP
= 24.9k, R
BOTTOM
= 11.3k
4. VTRIM1_CFG, R
TOP
= Open, R
BOTTOM
= 0Ω
The frequency and phase are set by NVM or by setting
V
IN
V
DD33
V
DD25
SGND
TG0
0.1µF
4.99k
0.1µF
1µF
1µF
L0, L1: VISHAY IHLP-4040DZ-11 1µH, 0.56µH
M1, M2: INFINEON BSC050N03LS
M3, M4: INFINEON BSC010NE2LSI
1µF
4700pF
0.22µF
0.22µF
2200pF
22µF
V
IN
6V TO 24V
10µF
+
530µF
D2
M2
M4
10k
15.8k
V
DD25
M1
M3
V
OUT1
1.8V
15A
4.99k 4.99k
2.0k
1µF
L1
0.56µH
L0
1.0µH
D1
TG1
BG0
SYNC
10k
24.9k
11.3k
10k
1µF
1.58k
23.2k
20k
12.7k
GPIO0
10k
GPIO1
10k
SDA
10k
SCL
10k
ALERT
10k
RUN0
FREQ_CFG
V
OUT0_CFG
V
OUT1_CFG
V
TRIM0_CFG
V
TRIM1_CFG
ASEL
10k
RUN1
WP
10k
2.0k 1.58k
SHARE_CLK
V
DD33
BG1
PGND
BOOST0 BOOST1
SW0 SW1
INTV
CC
LTC3880
TSNS0 TSNS1
I
THO
I
TH1
I
SENSEO
+
I
SENSE1
+
V
SENSEO
+
V
SENSE1
V
SENSEO
–
I
SENSEO
–
I
SENSE1
–
V
OUT0
3.3V
15A
V
OUT1
1.8V
15A
V
OUT1
1.8V
15A
+
530µF
3880 F27
220pF 220pF10nF
10nF
Figure 27. High Efficiency Dual 500kHz 3.3V/1.8V Step-Down Converter