Datasheet

LTC3880/LTC3880-1
54
3880fc
For more information www.linear.com/LTC3880
APPLICATIONS INFORMATION
to 80% of full-load current having a rise time of 1µs to
10µs will produce output voltage and I
TH
pin waveforms
that will give a sense of the overall loop stability without
breaking the feedback loop. Placing a power MOSFET with
a resistor to ground directly across the output capacitor
and
driving
the gate with an appropriate signal generator
is a practical way to produce to a load step. The MOSFET
+ R
SERIES
will produce output currents approximately
equal to V
OUT
/R
SERIES
. R
SERIES
values from 0.1Ω to 2Ω
are valid depending on the current limit settings and the
programmed output voltage. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
is why it is better to look at the I
TH
pin signal which is in
the feedback loop and is the filtered and compensated
control loop response. The gain of the loop will be in
-
creased by increasing R
C
and the bandwidth of the loop
will be increased by decreasing C
C
. If R
C
is increased by
the same factor that C
C
is decreased, the zero frequency
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
LOAD
to C
OUT
is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • C
LOAD
. Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
PC BOARD LAYOUT CHECKLIST
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 25. Figure 26 illustrates the
current waveforms present in the various branches of
the 2-phase synchronous regulators operating in the
continuous mode. Check the following in your layout:
1.
Are the top N-channel MOSFETs M1 and M2 located
within 1 cm of each other with a common drain con-
nection at C
IN
? Do not attempt to split the input de-
coupling for the two channels as it can cause a large
resonant loop.
2.
Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return of
C
INTVCC
must return to the combined C
OUT
(–) terminals.
The I
TH
traces should be as short as possible. The path
formed by the top N-channel MOSFET, Schottky diode
and the C
IN
capacitor should have short leads and PC
trace lengths. The output capacitor (–) terminals should
be connected as close as possible to the (–) terminals
of the input capacitor by placing the capacitors next to
each other and away from the Schottky loop described
above.
3. Does the LTC3880 V
SENSE
lines equal V
OUT
? V
OUT0
is
differential. V
OUT1
should reference the SGND (Pin 41)
to the Load 1 ground.
4. Are the I
SENSE
+
and I
SENSE
–
leads routed together with
minimum PC trace spacing? The filter capacitor between
I
SENSE
+
and I
SENSE
–
should be as close as possible to