Datasheet

LTC3880/LTC3880-1
28
3880fc
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OPERATION
log data is erased, or else the part will immediately issue
another fault log.
When the LTC3880 powers-up, it checks the NVM for
a valid fault log. If a valid fault log exists in NVM, the
“Valid Fault Log” bit in the STATUS_MFR_SPECIFIC com
-
mand will be set and an ALERT event will be generated.
Also, fault logging will be blocked until the LTC3880 has
received a MFR_FAULT_LOG_CLEAR command before
fault logging will be re-enabled.
The information is stored in EEPROM in the event of any fault
that disables the controller on either channel. An external
GPIOn pulling low will not trigger a fault logging event.
BUS TIMEOUT FAILURE
The LTC3880 implements a timeout feature to avoid hanging
the serial interface. The data packet timer begins at the first
START event before the device address write byte. Data
packet information must be completed within 25ms or
the LTC3880 will three-state the bus and ignore the given
data packet. Data packet information includes the device
address byte write, command byte, repeat start event
(if a read operation), device address byte read (if a read
operation), all data bytes and the PEC byte if applicable.
The LTC3880 allows longer PMBus timeouts for block read
data packets. This timeout is proportional to the length
of the block read. The additional block read timeout ap
-
plies primarily to the MFR_FAULT_LOG command. In no
circumstances will the timeout period be less than the
t
TIMEOUT_SMB
specification of 32ms (typical).
The user is encouraged to use as high a clock rate as
possible to maintain efficient data packet transfer between
all devices sharing the serial bus interface. The LTC3880
supports the full PMBus frequency range from 10kHz to
400kHz.
SIMILARITY BETWEEN PMBUS, SMBUS AND I
2
C
2-W
IRE INTERFACE
The PMBus 2-wire interface is an incremental extension
of the SMBus. SMBus is built upon I
2
C with some minor
differences in timing, DC parameters and protocol. The
PMBus/SMBus protocols are more robust than simple I
2
C
byte commands because PMBus/SMBus provide time-outs
to prevent bus hangs and optional packet error checking
(PEC) to ensure data integrity. In general, a master device
that can be configured for I
2
C communication can be
used for PMBus communication with little or no change
to hardware or firmware. Repeat start (restart) is not
supported by all I
2
C controllers but is required for SMBus/
PMBus reads. If a general purpose I
2
C controller is used,
check that repeat start is supported.
For a description of the minor extensions and exceptions
PMBus makes to SMBus, refer to PMBus Specification
Part 1 Revision 1.1: Paragraph 5: Transport.
For a description of the differences between SMBus and
I
2
C, refer to System Management Bus (SMBus) Speci-
fication Version 2.0: Appendix B—Differences Between
SMBus and I
2
C.
PMBUS SERIAL DIGITAL INTERFACE
The LTC3880 communicates with a host (master) using the
standard PMBus serial bus interface. The Timing Diagram,
Figure 5, shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines.
The LTC3880 is a slave device. The master can communicate
with the LTC3880 using the following formats:
n
Master transmitter, slave receiver
n
Master receiver, slave transmitter
The following PMBus protocols are supported:
n
Write Byte, Write Word, Send Byte
n
Read Byte, Read Word, Block Read
n
Alert Response Address
Figures 7-16 illustrate the aforementioned PMBus proto-
cols. All transactions support PEC (parity error check) and
GCP (group command protocol). The Block Read supports
255 bytes of returned data. For this reason, the PMBus
timeout may be extended when reading the fault log.
Figure 6 is a key to the protocol diagrams in this section.
PEC is optional.