Datasheet

LTC3880/LTC3880-1
25
3880fc
For more information www.linear.com/LTC3880
OPERATION
SERIAL INTERFACE
The LTC3880 serial interface is a PMBus compliant slave
device and can operate at any frequency between 10kHz
and 400kHz. The address is configurable using either the
NVM or an external resistor divider. In addition the LTC3880
always responds to the global broadcast address of 0x5A
(7 bit) or 0x5B (7 bit). Address 0x5A is not paged and
is performed on both channels. 0x5B respects the page
command. Because address 0x5A does not support page,
it can not be used for any paged reading commands.
The serial interface supports the following protocols defined
in the PMBus specifications: 1) send command, 2) write
byte, 3) write word, 4) group, 5) read byte, 6) read word
and 7) read block. All read operations will return a valid
PEC if the PMBus master requests it. If the PEC_REQUIRED
bit is set in the MFR_CONFIG_ALL_LTC3880 command,
the PMBus write operations will not be acted upon until
a valid PEC has been received by the LTC3880.
Communication Failure
PEC write errors (if PEC_REQUIRED is active), attempts
to access unsupported commands, or writing invalid data
to supported commands will result in a CML fault. The
CML bit is set in the STATUS_BYTE and STATUS_WORD
commands, the appropriate bit is set in the STATUS_CML
command, and the ALERT pin is pulled low.
DEVICE ADDRESSING
The LTC3880 offers five different types of addressing over
the PMBus interface, specifically: 1) global, 2) device, 3)
channel, 4) rail addressing and 5) alert response address
(ARA).
Global addressing provides a means of the PMBus master to
address all LTC3880 devices on the bus. The LTC3880 global
address is fixed 0x5A (7 bit) or 0xB4 (8 bit) and cannot be
disabled. Commands sent to the global address act the
same as if PAGE is set to a value of 0xFF. Commands sent are
written to both channels simultaneously. Global command
0x5B (7 bit) or 0xB6 (8 bit) is paged and allows channel
specific command of all LTC3880 devices on the bus.
Device addressing provides the standard means of the
PMBus master communicating with a single instance
of an LTC3880. The value of the device address is set
by a combination of the ASEL configuration pin and the
MFR_ADDRESS command. When this addressing means
is used, the PAGE command determines the channel being
acted upon. Device addressing can be disabled by writing
a value of 0x80 to the MFR_ADDRESS.
Channel addressing provides a means for the PMBus
master addressing a single channel of the LTC3880
without using the PAGE command. The value assigned
to the paged MFR_CHANNEL_ADDRESS determines the
specific channel the user wishes to act upon. Example: If
MFR_CHANNEL_ADDRESS for page 0 is set to 0x57 and
the MFR_CHANNEL_ADDRESS for page 1 is set to 0x54,
the user can address channel 0 of the device by performing
PMBus device commands using address 0x57 (7 bit). The
user can address channel 1 of the device by performing
PMBus device commands using address 0x54 (7 bit). This
eliminates the user from first assigning the PAGE command
and then the command to be acted upon.
Rail addressing provides a means for the PMBus master
addressing a set of channels connected to the same output
rail, simultaneously. This is similar to global addressing,
however, the PMBus address can be dynamically assigned
by using the MFR_RAIL_ADDRESS command. The MFR_
RAIL_ADDRESS is paged, so channels can be indepen
-
dently assigned to a specific rail. It is recommended that rail
addressing should be limited to command write operations.
All five means of PMBus addressing require the user to
employ disciplined planning to avoid addressing conflicts.
RESPONSES TO V
OUT
AND I
OUT
FAULTS
V
OUT
OV and UV conditions are monitored by comparators.
The OV and UV limits are set in three ways.
n
As a Percentage of the V
OUT
if Using the Resistor Con-
figuration Pins
n
In NVM if Either Programmed at the Factory or Through
the GUI
n
By PMBus Command