Datasheet

LTC3880/LTC3880-1
15
3880fc
For more information www.linear.com/LTC3880
BLOCK DIAGRAM
16-BIT
ADC
8-BIT V
IN
DAC
PWM1
+
–
–
+
–
–
+
+
+
+
–
–
PWM0
–
+
V
SENSE1
–
+
I
SENSE1
–
–
I
SENSE1
+
+
8:1
MUX
TMUX
2µA
I
LIM
DAC
(3 BITS)
OV
8-BIT
OV
DAC
8-BIT
UV
DAC
12-BIT
SET POINT
DAC
UVEA
+
0.56V
1.22V
BURST
I
TH0
R
C
C
C1
30µA
–
+
–
+
AO
R
R
9R
2R
SGND
PWM
CLOCK
V
OUT0_CFG
R
V
SENSE0
+
SGND
TSNS0
V
SENSE0
–
NO DIFF AMP ON CH1
R
SWITCH
LOGIC
AND
ANTI-
SHOOT-
THROUGH
OV
RUN
SS
UVLO
REV
UV
ON
FCNT
1
2
41
40
18
V
OUT1_CFG
19
V
TRIM0_CFG
20
V
TRIM1_CFG
21
FREQ_CFG
17
ASEL
3880 F01
16
13
12
15
14
PGND
C
VCC
34
BG0
D
B
M1
V
IN
C
IN
INTV
CC
/EXTV
CC
V
DD33
36
I
SENSE0
–
7
I
SENSE0
+
6
SW0
39
TG0 C
B
38
BOOST0
37
V
DD33
25
INTV
CC
/EXTV
CC
(LTC3880-1)
33
M2
C
OUT
V
OUT0
+
3.3V
SUBREG
2.5V
SUBREG
V
IN
35
5V REG
38R
R
SGND
–
+
–
+
–
+
1
71.1k
ACTIVE
CLAMP
UVLOINTV
CC
SLOPE
COMPENSATION
SLAVE
V
DD33
MISO
MOSICLK
MASTER
RAM
RUN0
RUN1
24
SHARE_CLK
GPIO0
GPIO1
EEPROM
MAIN
CONTROL
PROGRAM
ROM
V
DD33
COMPARE
I
LIM
RANGE SELECT
HI: 1:1
LO: 1:1.5
3k
I
CMP
I
REV
5
+
–
+
–
V
IN
ON/OFF
+
–
S
REF
V
STBY
SGND
Q
PWM_CLOCK
R
PHASE DET
V
CO
PHASE SELECTOR
CLOCK DIVIDER
SINC
3
UVLO
OSC
(32MHz)
CONFIG
DETECT
CHANNEL
TIMING
MANAGEMENT
11
10
9
23
WP
SCL
SDA
ALERT
PMBus
INTERFACE
(400kHz
COMPATIBLE)
SYNC
SGND
M3
SGND
V
DD33
8
V
DD25
22
V
DD25
+
LTC3880
ONLY
19R
R
Figure 1. Block Diagram
(One of two channels (CH0) shown)