Datasheet

LTC3880/LTC3880-1
14
3880fc
For more information www.linear.com/LTC3880
PIN FUNCTIONS
FREQ_CFG (Pin 17): Frequency or Phase Set/Select Pin.
Connect a ±1% resistor divider between the chip V
DD25
FREQ_CFG and SGND in order to select switching frequency
or phase. If the pin is left open, the IC will use the value
programmed in the NVM. Minimize capacitance when the
pin is open to assure accurate detection of the pin state.
V
OUT0_CFG
/V
OUT1_CFG
(Pin 18/Pin 19): Output Voltage
Select Pin. Connect a ±1% resistor divider between the
chip V
DD25
V
OUT
n_CFG and SGND in order to select output
voltage. This voltage can be adjusted with the V
TRIM
n_CFG
pins. If the pin is left open, the IC will use the value pro-
grammed in the NVM. Minimize capacitance when the
pin is open to assure accurate detection of the pin state.
V
TRIM0_CFG
/V
TRIM1_CFG
(Pin 20/Pin 21): Voltage Trim
Select Pin. Connect a ±1% resistor divider between the
chip V
DD25
V
TRIM
n_CFG and SGND in order to adjust
the output voltage set point. The V
TRIM
n_CFG settings
in conjunction with the V
OUT
n_CFG setting adjusts the
voltage set point. If the pin is left open, the IC will either
not modify the V
OUT
n_CFG setting or use NVM. Minimize
capacitance when the pin is open to assure accurate de-
tection of the pin state.
V
DD25
(Pin 22): Internally Generated 2.5V power Supply
Output Pin. Bypass this pin to SGND with a low ESR 1µF
capacitor. Do not load this pin with external current except
for the ±1% resistor dividers required for the configura
-
tion pins.
WP (Pin 23): Write Protect Pin Active High. An internal
10µA current sour
ce pulls the pin to V
DD33
. If WP is high,
the PMBus writes are restricted.
SHARE_CLK (Pin 24): Share Clock, Bidirectional Open-
Drain Clock Sharing Pin. Nominally 100kHz. Used to
synchronize the timing between multiple LTC3880s. Tie all
SHARE_CLK pins together. All LTC3880s will synchronize
to the fastest clock. A pull-up resistor to 3.3V is required.
V
DD33
(Pin 25): Internally Generated 3.3V Power Supply
Output Pin. Bypass this pin to SGND with a low ESR 1µF
capacitor. Do not load this pin with external current except
for the pull-up resistors required for GPIOn, SCLK, SYNC
and possibly RUNn, ALERT, SDA and SCL.
V
SENSE1
(Pin 27): Channel 1 Voltage Sense Input. This
input voltage is referenced to the SGND pin.
INTV
CC
(Pin 33) LTC3880: Internal Regulator 5V Out-
put. The control circuits are powered from this voltage.
Decouple this pin to PGND with a minimum of 4.7µF low
ESR tantalum or ceramic capacitor
.
EXT
V
CC
(Pin 33) LTC3880-1: External Regulator 5V
input. The control circuits are powered from this voltage.
Decouple this pin to PGND with a minimum of 4.7µF low
ESR tantalum or ceramic capacitor.
PGND (Pin 34):
Power Ground Pin. Connect this pin closely
to the sources of the bottom N-channel MOSFETs, the (–)
terminal of C
VCC
and the (–) terminal of C
IN
.
V
IN
(Pin 35): Main Input Supply. Decouple this pin to
PGND with a capacitor (0.1µF to 1µF). For applications
where the main input power is 5V, tie the V
IN
and INTV
CC
pins together.
BG0/BG1 (Pin 36/Pin 32): Bottom Gate Driver Outputs.
These pins drive the gates of the bottom N-Channel
MOSFETs between PGND and INTV
CC
.
BOOST0/BOOST1 (Pin 37/Pin 31): Boosted Floating Driver
Supplies. The (+) terminal of the booststrap capacitors
connect to these pins. These pins swing from a diode
voltage drop below INTV
CC
up to V
IN
+ INTV
CC
.
TG0/TG1 (Pin 38/Pin 30): Top Gate Driver Outputs. These
are the outputs of floating drivers with a voltage swing equal
to INTV
CC
superimposed on the switch node voltages.
SW0/ SW1 (Pin 39/Pin 29): Switch Node Connections to
Inductors. Voltage swings at the pins are from a Schottky
diode (external) voltage drop below ground to V
IN
.
TSNS0/TSNS1 (Pin 40/Pin 28): Channel 0,1 External
Diode Temperature Sense. Connect to the anode of a diode
connected PNP transistor and star connect the cathode
to SGND in order to sense remote temperature. If exter
-
nal temperature sense elements are not installed, short
pin to ground and set the UT_F
AUL
T_LIMIT to –275°C,
IOUT_CAL_GAIN set to zero and the UT_FAULT_RESPONSE
to ignore.
SGND (Exposed Pad Pin 41): Signal Ground. All small-
signal and compensation components should connect to
this ground, which in turn connects to PGND at one point.