Datasheet

LTC3878
11
3878fa
The resulting power dissipation in the MOSFETs at maxi-
mum output current are:
P D I R
V
TOP TOP OUT MAX TOP DS ON MAX
=
+
• • •
( ) ( ) ( )( )
2
ρ
τ
IIN
OUT MAX
MILLER
TGHIGH
INTVC
I
C
DR
V
2
2
( )






( )
CC MILLER
TGLOW
MILLER
OSC
BOT BO
V
DR
V
f
P D
–
+






=
TT OUT MAX BOT DS ON MAX
I R• • •
( ) ( ) ( )( )
2
ρ
τ
DR
TGHIGH
is pull-up driver resistance and DR
TGLOW
is the
TG driver pull-down resistance. V
MILLER
is the Miller ef-
fect V
GS
voltage and is taken graphically from the power
MOSFET data sheet.
MOSFET input capacitance is a combination of several
components but can be taken from the typical “gate charge”
curve included on the most data sheets (Figure 2). The
curve is generated by forcing a constant input current
into the gate of a common source, current source, loaded
stage and then plotting the gate versus time. The initial
slope is the effect of the gate-to-source and gate-to-drain
capacitance. The flat portion of the curve is the result of the
Miller multiplication effect of the drain-to-gate capacitance
as the drain drops the voltage across the current source
load. The upper sloping line is due to the drain-to-gate
accumulation capacitance and the gate-to-source capaci
-
tance. The
Miller charge (the increase in coulombs on the
horizontal axis from a to b while the curve is flat) is speci
-
fied from
a given V
DS
drain voltage, but can be adjusted
for different V
DS
voltages by multiplying by the ratio of
the application V
DS
to the curve specified V
DS
values. A
way to estimate the C
MILLER
term is to take the change in
gate charge from points a and b or the parameter Q
GD
on
a manufacturers data sheet and divide by the specified
V
DS
test voltage, V
DS(TEST)
.
C
Q
V
MILLER
GD
DS TEST
=
( )
C
MILLER
is the most important selection criteria for deter-
mining the transition loss term in the top MOSFET but is
not directly specified on MOSFET data sheets.
Both MOSFETs have I
2
R power loss, and the top MOSFET
includes an additional term for transition loss, which are
highest at high input voltages. For V
IN
< 20V, the high cur-
rent efficiency generally improves with larger MOSFETs,
while for V
IN
> 20V, the transition losses rapidly increase
to the point that the use of a higher R
DS(ON)
device with
lower C
MILLER
actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
Operating Frequency
The choice of operating frequency is a tradeoff between
efficiency and component size. Lowering the operating fre
-
qu
ency improves efficiency by reducing MOSFET switching
losses but requires larger inductance and/or capacitance
to maintain low output ripple voltage. Conversely, raising
the operating frequency degrades efficiency but reduces
component size.
The operating frequency of LTC3878 applications is de
-
termined implicitly by the one-shot timer that controls the
on-time, t
ON
, of the top MOSFET switch. The on-time is
set by the current into the I
ON
pin according to:
t
V
I
pF
ON
ION
=
( )
0 7
10
.
Tying a resistor R
ON
from V
IN
to the I
ON
pin yields an
on-time inversely proportional to V
IN
. For a step-down
converter, this results in pseudo fixed frequency operation
as the input supply varies.
f
V
V R pF
Hz
OP
OUT
ON
=
( )
0 7 10. •
[ ]
applicaTions inForMaTion
Figure 2. Gate Charge Characteristic
+
–
V
DS
V
IN
3878 F02
V
GS
MILLER EFFECT
Q
IN
a b
C
MILLER
= (Q
B
– Q
A
)/V
DS
V
GS
V
+
–