Datasheet

LTC3878
18
3878fa
V
RNG
sets current limit by fixing the maximum peak V
DS
voltage on the bottom MOSFET switch. As a result, the
average DC current limit includes significant temperature
and component variability. Design to guarantee that the
average DC current limit will always exceed the rated oper
-
ating output
current by assuming worst-case component
tolerance and temperature.
The worst-case minimum INTV
CC
is 5.15V. The bottom
MOSFET worst-case R
DS(ON)
is 3.9mΩ and the junction
temperature is 80°C above a 70°C ambient with ρ
150°C
=
1.5. Set T
ON
equal to the minimum specification of 15%
low and the inductor 15% high.
By setting I
LIMIT
equal to 15A we get 79mV for peak V
DS
voltage which corresponds to a V
RNG
equal to 592mV:
V A A
m
V
DS
=






15
1
2
5 1
0 85
1 15
3 9
5 15
5 3
– • . •
.
.
.
.
.
Ω
VV
V V
RNG DS
• .
. •
1 5
7 5=
Verify that the calculated nominal T
J
is less than the
assumed worst-case T
J
in the bottom MOSFET:
P
V V
V
A m W
T C
BOT
J
=
( )
=
= ° +
28 1 2
28
15 1 5 3 9 1 25
70 1
2
– .
• . • . .Ω
.. • /25 40 120W C W C° = °
B ecause the top MOSFET is on for a short time, an
RJK0305DPB (R
DS(ON)
= 10mΩ (nominal) 13mΩ (maxi-
mum) (C
MILLER
= Q
GD
/10V = 150pF, V
BOOST
= 5V), V
GS
=
4.5V, V
MILLER
= 3V, θ
JA
= 40°C/W) is sufficient. Checking its
power dissipation at current limit with = ρ
100°C
= 1.4:
P
V
V
A m V
A
TOP
=
( )
+
( )






1 2
28
15 1 4 13 28
15
2
150
2 2
.
• . • Ω
ppF
V V V
kHz
W W
( )
−
+






= + =
2 5
5 3
1 2
3
400
0 18 0 58 0
. .
. .
Ω Ω
..
. • /
65
70 0 76 40 100
W
T C W C W C
J
= ° + ° = °
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention
to heat sinking will be necessary.
Select C
IN
to give an RMS current rating greater than 4A
at 85°C. The output capacitor C
OUT1
is chosen for a low
ESR of 4.5mΩ to minimize output voltage changes due to
inductor ripple current and load steps. The output voltage
ripple is given as:
∆ ∆
Ω
V I ESR
m mV
OUT RIPPLE L MAX( ) ( )
. • .
=
( )
= =5 1 4 5 23
However, a 0A to 10A load step will cause an output
change of up to:
∆ ∆
Ω
V I ESR
A m mV
OUT STEP LOAD( )
• .
=
( )
= =10 4 5 45
Optional 2 × 47µF ceramic output capacitors are included
to minimize the effect of ESR and ESL in the output ripple
and to improve load step response.
PC Board Layout Checklist
The LTC3878 PC board layout can be designed with or
without a ground plane. A ground plane is generally pre
-
ferred
based on performance and noise concerns.
When using a ground plane, use a dedicated ground plane
layer. In addition, for high current it is recommended to
use a multilayer board to help with heat sinking power
components.
l The ground plane layer should have no traces and be
as close as possible to the routing layer connecting the
power MOSFET’s.
l Place LTC3878 Pins 9 to 16 facing the power compo-
nents. Keep components connected to Pin 1 close to
LTC3878 (noise sensitive components).
l Place C
IN
, C
OUT
, MOSFETs, D
B
and inductor all in one
compact area. It may help to have some components
on the bottom side of the board.
l Use an immediate via to connect components to the
ground plane SGND and PGND of LTC3878. Use several
larger vias for power components.
l Use compact switch node (SW) plane to improve cool-
ing of the MOSFETs and to keep EMI down.
applicaTions inForMaTion