Datasheet

LTC3876
41
3876f
APPLICATIONS INFORMATION
Figure 12. Recommended PCB Layout Diagram
• Place the resistor feedback divider R
FB1
, R
FB2
close to
V
OUTSENSE1
+
and V
OUTSENSE1
–
pins for channel 1, or
V
FB2
pin for channel 2, so that the feedback voltage
tapped from the resistor divider will not be disturbed by
noise sources. Route remote sense PCB traces (use a
pair of wires closely together for differential sensing in
channel 1) directly to the terminals of output capacitors
for best output regulation.
• Place decoupling capacitors C
ITH2
next to the ITH and
SGND pins with short, direct trace connections.
• Use sufficient isolation when routing a clock signal into
the MODE/PLLIN pin or out of the CLKOUT pin, so that
the clock does not couple into sensitive pins.
• Place the ceramic decoupling capacitor C
INTVCC
between
the INTV
CC
pin and SGND and as close as possible to
the IC.
• Place the ceramic decoupling capacitor C
DRVCC
close
to the IC, between the combined DRV
CC1,2
pins and
PGND.
• Filter the V
IN
input to the LTC3876 with an RC filter.
Place the filter capacitor close to the V
IN
pin.
• If vias have to be used, use immediate vias to connect
components to the SGND and PGND planes of LTC3876.
Use multiple large vias for power components.
SENSE2
–
LTC3876
SENSE2
+
VTTSNS
ITH2
C
ITH1(2)
C
ITH2(2)
LOCALIZED
SGND TRACE
PGOOD2
BOOST2
TG2
C
B2
D
B2
D
B1
R
INTVCC
SW2
DRV
CC2
EXTV
CC
V
IN
DRV
CC1
BG1
SW1
TG1
BOOST1
PGOOD1
RUN1
DTR1
PGND
INTV
CC
C
VCC
BG2
C
INTVCC
C
VIN
R
VIN
C
DRVCC
C
B1
C
IN
CERAMIC
CERAMIC
MT2
MB2
MT1
MB1
+
V
IN
L2
L1
C
OUT2
V
OUT2
GND
V
OUT1
+
C
OUT1
+
R
SENSE1
3876 F12
R
SENSE2
RT
R
T
V
RNG2
PHASMD
MODE/PLLIN
CLKOUT
SGND
V
RNG1
R
ITH1(2)
C
ITH2(1)
C
ITH1(1)
C
SS1
R
FB1(1)
R
ITH1(1)
ITH1
TRACK/SS1
V
OUTSENSE1
+
V
OUTSENSE1
–
SENSE1
+
SENSE1
–
R
ITH2(1)
R
FB2(1)