Datasheet

LTC3876
38
3876f
The DCR sense filter is designed using a simple RC filter
across the inductor. If the inductor value and DCR is known,
choose a sense filter C and calculate filter resistance.
Channel 1 DCR filter resistor R
DCR1
:
R
DCR1
=
L1
DCR•C
DCR
=
0.47µH
0.8mΩ •0.1µF
= 5.9k
Channel 2 DCR filter resistor R
DCR2
:
R
DCR1
=
L1
DCR•C
DCR
=
0.47µH
1.72mΩ •0.1µF
= 2.74k
The external N-channel MOSFETs are chosen based
on current capability and efficiency. The Renesas
RJK0305DBP (R
DS(ON)
= 13m(maximum), C
MILLER
= 150pF,
VGS = 4.5V, V
MILLER
= 3V, θ
JA
= 40°C/W, T
J(MAX)
= 150°C)
is chosen for the top MOSFET (main switch). The Renesas
RJK0330DBP (R
DS(ON)
= 3.9m(maximum), V
GS
= 4.5V,
θ
JA
= 40°C/W, T
J(MAX)
=150°C) is chosen for the bottom
MOSFET (synchronous switch).The power dissipation for
each MOSFET can be calculated for V
IN
= 14V and typical
T
J
=125°C.
The power dissipation for V
IN
= 14V and T
J
=125°C for
the top MOSFET is:
P
TOP
=
1.5V
14V
20A
2
1+0.4% 125°C–25°C 0.013Ω +
14V
2
20A
2
150pF
2.5Ω
5.3V–3V
+
1.2Ω
3V
⎛
⎝
⎜
⎛
⎝
⎜
⎞
⎠
⎟
⎞
⎠
⎟
400kHz
= 0.78W+0.17W =0.95W
(
)
(
)
(
)
(
)
(
)
(
)
(
)
The power dissipation for V
IN
= 14V and T
J
=125°C for
2X bottom MOSFETs is:
P
BOT
=
14V–1.5V
14V
20A
2X
2
1+0.4% 125°C–25°C 0.0039Ω
= 0.4875W
⎛
⎝
⎜
⎞
⎠
⎟
(
)
(
)
(
)
The resulting junction temperatures for ambient tempera-
ture T
A
= 75°C are:
T
J(TOP)
= 75°C + (0.95W)(40°C/W) = 113°C
T
J(BOT)
= 75°C + (0.975W)(40°C/W) = 94.5°C
These numbers show that careful attention should be paid
to proper heat sinking when operating at higher ambient
temperatures.
Select C
IN
capacitors to give ample capacitance and RMS
ripple current rating. Consider worst-case duty cycles per
Figure 6. If operated at steady-state with SW nodes fully
interleaved, the two channels would generate not more
than 7.5A RMS at full load. In this design example, 2X
10µF 25V X5R ceramic capacitors are put in parallel to take
the RMS ripple current with 330µF aluminum electrolytic
bulk capacitors for stability. For 10µF 1210 X5R ceramic
capacitors, try to keep the ripple current less than 3A RMS
through each device. The bulk capacitor is chosen for
RMS rating per simulation with the circuit model provided.
The power supply output capacitor’s C
OUT
are chosen
for a low ESR. For channel 1 VDDQ, the output capacitor
SANYO 2R5TPE330M9, has an ESR of 9m which results
in 4.5m for two in parallel. For channel 2 VTT, the output
capacitor SANYO 2R5TPE330M9, has an ESR of 9m.
The output ripple for each channel is given as:
∆VDDQ(RIPPLE) = ∆I
L(MAX)
(ESR)
= (7.12A) • (4.5m) = 32mV
∆VTT(RIPPLE) = ∆I
L(MAX)
(ESR)
= (3.78A) • (9m) = 34mV
A 0A to 10A load step in VDDQ will cause an output change
of up to:
∆VDDQ(STEP) = ∆I
LOAD
(ESR) = 10A • 0.0045m =
45mV
A 0A to 5A load step in VTT will cause an output change
of up to:
∆VTT(STEP) = ∆I
LOAD
(ESR) = 5A • 0.009m = 45mV
Optional 100µF ceramic output capacitors are included
to minimize the effect of ESL in the output ripple and to
improve load step response.
APPLICATIONS INFORMATION