Datasheet

LTC3866
27
3866fb
adequate starting point for most applications. The ITH series
R
C
-C
C
filter sets the dominant pole-zero loop compensation.
The values can be modified slightly (from 0.5 to 2 times
their suggested values) to optimize transient response
once the final PC layout is done and the particular output
capacitor type and value have been determined. The output
capacitors need to be selected because the various types
and values
determine the loop gain and phase. An output
current pulse of 20% to 80% of full-load current having a
rise time of 1µs to 10µs will produce output voltage and
ITH pin waveforms that will give a sense of the overall
loop stability without breaking the feedback loop. Placing
a power MOSFET directly across the output capacitor and
driving the gate with an appropriate signal generator is a
practical way to produce a realistic load step condition. The
initial output voltage step resulting from the step change
in output current may not be within the bandwidth of the
feedback loop, so this signal cannot be used to determine
phase margin. This is why it is better to look at the ITH
pin signal which is in the feedback loop and is the filtered
and compensated
control loop response. The gain of the
loop will be increased by increasing R
C
and the bandwidth
of the loop will be increased by decreasing C
C
. If R
C
is
increased by the same factor that C
C
is decreased, the
zero frequency will be kept the same, thereby keeping the
phase shift the same in the most critical frequency range
of the feedback loop. The output
voltage settling behavior
is related to the stability of the closed-loop system and
will demonstrate the actual overall supply performance.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
LOAD
to C
OUT
is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • C
LOAD
. Thus a 10µF capacitor would
require
a 250µs rise time, limiting the charging current
to about 200mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 14. Check the following in the
PC layout:
1. The INTV
CC
decoupling capacitor should be placed
immediately adjacent to the IC between the INTV
CC
pin
and PGND plane. A 1µF ceramic capacitor of the X7R
or X5R type is small enough to fit very close to the IC
to minimize the ill effects of the large current pulses
drawn to drive the bottom MOSFETs. An additional
4.7µF to 10µF of ceramic, tantalum or
other very low
ESR capacitance is recommended in order to keep the
internal IC supply quiet.
APPLICATIONS INFORMATION
Figure 14. Branch Current Waveforms
+
R
IN
V
IN
V
OUT
C
IN
+
C
OUT
D1
SW2
SW1
L1
DCR
R
L
3866 F14
BOLD LINES INDICATE HIGH, SWITCHING CURRENTS. KEEP LINES TO A MINIMUM LENGTH