Datasheet

LTC3865/LTC3865-1
32
3865fb
APPLICATIONS INFORMATION
With I
LIM
fl oating, the equivalent R
SENSE
resistor value
can be calculated by using the minimum value for the
maximum current sense threshold (44mV).
R
V
I
I
SENSE EQUIV
SENSE MIN
LOAD MAX
L NOM
()
()
()
(
=
+
Δ
))
.
.
2
44
5
15
2
77=
+
≅
mV
A
A
mΩ
The equivalent R
SENSE
is the same for Channel 2.
The Coiltronics (Cooper) HCP0703-2R2 (20m DCR
MAX
at 20°C) and HCP0703-3R3 (30mΩ DCR
MAX
at 20°C) are
chosen. At 100°C, the estimated maximum DCR values are
26.4mΩ and 39.6mΩ. The divider ratios are:
R
R
DCR at T
m
m
D
SENSE EQUIV
MAX L MAX
==
()
()
.
.
77
26 4
Ω
Ω
==
≅
03
77
39 6
02
.;
.
.
.and
m
m
Ω
Ω
For each channel, 0.1µF is selected for C1.
RR
L
DCR at C C
H
mF
MAX
12
20 1
22
20 0 1
1
||
()•
.
•.
=
°
=
=
μ
μΩ
.. ;
.
•.
.1
33
30 0 1
11kand
H
mF
k
μ
μΩ
=
For channel 1, the DCR
SENSE
fi lter/divider values are:
R
RR
R
k
k
R
RR
R
k
D
D
D
1
12
11
02
55
2
1
1
55
==≅
=
−
=
||
.
.
.;
•.•
002
102
137
.
.
.
−
≅ k
The power loss in R1 at the maximum input voltage is:
PR
VVV
R
VV
LOSS
IN MAX OUT OUT
1
1
20 3 3 3
=
−
=
−
()•
(.)•
()
..
.
3
55
10
V
k
mW=
The respective values for Channel 2 are R1 = 3.66k,
R2 = 1.57k; and P
LOSS
R1 = 8mW.
Burst Mode operation is chosen for high light load effi ciency
(Figure 15) by fl oating the MODE/PLLIN pin. Power loss
due to the DCR sensing network is slightly higher at light
loads than would have been the case with a suitable sense
resistor (8mΩ). At heavier loads, DCR sensing provides
higher effi ciency.
The power dissipation on the topside MOSFET can be easily
estimated. Choosing a Siliconix Si4816BDY dual MOSFET
results in: R
DS(ON)
= 0.023Ω/0.016Ω, C
MILLER
≅ 100pF.
At maximum input voltage with T(estimated) = 50°C:
P
V
V
CC
MAIN
=
()
+°°
[]
33
20
5 1 0 005 50 25
00
2
.
(. )( – )•
.
223 20
5
2
2 100
1
523
1
2
2
Ω
()
+
()
⎛
⎝
⎜
⎞
⎠
⎟
Ω
()( )
+
V
A
pF •
–. .. 3
500 186
⎡
⎣
⎢
⎤
⎦
⎥
()
=kHz mW
LOAD CURRENT (mA)
0.01
70
EFFICIENCY (%)
POWER LOSS (mW)
80
90
0.1 1 10
60
50
40
100
0.1
1
0.01
10
3865 F16
DCR
8m
POWER LOSS
EFFICIENCY
Figure 15. Design Example Effi ciency vs Load