Datasheet

LTC3865/LTC3865-1
24
3865fb
APPLICATIONS INFORMATION
Fault Conditions: Current Limit and Current Foldback
The LTC3865/LTC3865-1 include current foldback to help
limit load current when the output is shorted to ground.
If the output falls below 50% of its nominal output level,
then the maximum sense voltage is progressively lowered
from its maximum programmed value to one-third of the
maximum value. Foldback current limiting is disabled
during the soft-start or tracking up. Under short-circuit
conditions with very low duty cycles, the LTC3865 will begin
cycle skipping in order to limit the short-circuit current.
In this situation the bottom MOSFET will be dissipating
most of the power but less than in normal operation. The
short-circuit ripple current is determined by the minimum
on-time t
ON(MIN)
of the LTC3865/LTC3865-1 (≈ 90ns), the
input voltage and inductor value:
ΔIt
V
L
LSC ONMIN
IN
() ( )
•=
The resulting short-circuit current is:
I
V
R
I
SC
SENSE MAX
SENSE
LSC
=
13
1
2
/
–
()
()
Δ
Phase-Locked Loop and Frequency Synchronization
The LTC3865/LTC3865-1 have a phase-locked loop (PLL)
comprised of an internal voltage-controlled oscillator (V
CO
)
and a phase detector. This allows the turn-on of the top
MOSFET of controller 1 to be locked to the rising edge of an
external clock signal applied to the MODE/PLLIN pin. The
turn-on of controller 2’s top MOSFET is thus 180 degrees
out-of-phase with the external clock. The phase detector
is an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complementary
current sources that charge or discharge the internal fi lter
network. There is a precision 7.5µA of current fl owing out
of FREQ pin. This allows the user to use a single resistor
to SGND to set the switching frequency when no external
clock is applied to the MODE/PLLIN pin. The internal switch
between FREQ pin and the integrated PLL fi lter network is
on, allowing the fi lter network to be at the same voltage
potential as of FREQ pin. The relationship between the volt-
age on the FREQ pin and the operating frequency is shown
in Figure 10 and specifi ed in the Electrical Characteristic
table. If an external clock is detected on the MODE/PLLIN
pin, the internal switch mentioned above will turn off and
isolate the infl uence of FREQ pin. Note that the LTC3865 can
only be synchronized to an external clock whose frequency
is within range of the LTC3865/LTC3865-1’s internal V
CO
.
This is guaranteed to be between 250kHz and 770kHz. A
simplifi ed block diagram is shown in Figure 11.
FREQ PIN VOLTAGE (V)
0
FREQUENCY (kHz)
0.5 1 1.5 2
3865 F10
2.5
0
100
300
400
500
900
800
700
200
600
DIGITAL
PHASE/
FREQUENCY
DETECTOR
SYNC
VCO
2.4V 5V
7.5µA
R
SET
3865 F11
FREQ
EXTERNAL
OSCILLATOR
MODE/
PLLIN
Figure 10. Relationship Between Oscillator
Frequency and Voltage at the FREQ Pin
Figure 11. Phase-Locked Loop Block Diagram