Datasheet
LTC3865/LTC3865-1
10
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MODE/PLLIN (Pin 27/Pin 36): Force Continuous Mode,
Burst Mode or Pulse-Skip Mode Selection Pin and External
Synchronization Input to Phase Detector Pin. Connect this
pin to SGND to force both channels in continuous mode of
operation. Connect to INTV
CC
to enable pulse-skip mode of
operation. Leaving the pin fl oating will enable Burst Mode
operation. A clock on the pin will force the controller into
continuous mode of operation and synchronize the internal
oscillator with the clock on this pin.
FREQ (Pin 29/Pin 38): This pin sets the frequency of the
internal oscillator. A constant current of 7.5µA is fl owing
out of this pin and a resistor connected to this pin sets
its DC voltage, which in turn, sets the frequency of the
internal oscillator.
RUN1, RUN2 (Pins 30, 11/Pins 1, 17): Run Control
Inputs. A voltage above 1.22V on either pin turns on the IC.
However, forcing either of these pins below 1.22V causes
the IC to shut down the circuitry required for that particular
channel. There are 1µA pull-up currents for these pins.
Once the RUN pin rises above 1.22V, an additional 4.5µA
pull-up current is added to the pin.
PIN FUNCTIONS
(QFN/TSSOP)
SENSE1
+
, SENSE2
+
(Pins 31, 10/Pins 2, 16): Current
Sense Comparator Inputs. The (+) inputs to the current
comparators are normally connected to DCR sensing
networks or current sensing resistors.
SENSE1
–
, SENSE2
–
(Pins 32, 9/Pin 3, 15): Current Sense
Comparator Inputs. The (–) inputs to the current compara-
tors are connected to the outputs.
SGND (Pin 33/Pin 8): Signal Ground. All small-signal
components and compensation components should
connect to this ground, which in turn connects to PGND
at one point. Pin 33 is the Exposed Pad and available for
QFN package.
SGND (Exposed Pad Pin 33/ Exposed Pad Pin 39): Signal
Ground. Must be soldered to PCB, providing a local ground
for the control components of the IC, and be tied to the
PGND pin under the IC.
PGND1, PGND2 (NA/Pins 32, 26): Power Ground Pin.
Connect this pin closely to the sources of the bottom
N-channel MOSFETs, the (–) terminal of C
VCC
and the (–)
terminal of C
IN
.