Datasheet

LTC3864
26
3864f
R
PGD2
549k
MP
D1
L1
22µH
CAP
C
CAP
0.1µF
C
IN2
4.7µF
C
IN1
33µF
63V
PGND
*V
OUT
FOLLOWS V
IN
WHEN 3.5V ≤ V
IN
≤ 12V
LTC3864
3864 TA04a
SS
ITH
FREQ
SGND
RUN
V
IN
MODE/PLLN
SENSE
GATE
PGOOD
V
FB
R
SENSE
30mΩ
R
ITH
11.3k
R
FB2
845k
10µF
×2
V
OUT
*
12V
2A
R
FB1
60.4k
V
IN
12V TO 58V
C
VIN
0.1µF
C
ITH1
3300pF
C
ITH2
100pF
+
C
IN1
: SANYO 63ME33AX
D1: DIODES INC SBR3U100LP
L1: TOKO 1217AS-H-220M
MP: VISHAY/SILICONIX SI7465DP
R
PGD1
402k
TYPICAL APPLICATIONS
12V to 58V Input, 12V/2A Output at 535kHz
Efficiency
DE/UE Package
12-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1695 Rev D)
4.00 ±0.10
(2 SIDES)
3.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A VARIATION OF VERSION
(WGED) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.40 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.70 ± 0.10
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
2.50 REF
16
127
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(UE12/DE12) DFN 0806 REV D
3.30 ±0.10
0.25 ± 0.05
0.50 BSC
2.50 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.20 ±0.05
0.70 ±0.05
3.60 ±0.05
PACKAGE
OUTLINE
1.70 ± 0.05
3.30 ±0.05
0.50 BSC
0.25 ± 0.05
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LOAD CURRENT (A)
0.01
50
EFFICIENCY (%)
80
70
60
90
0.1 1
3864 TA04b
PULSE-SKIPPING
Burst Mode
OPERATION
V
IN
= 48V
V
OUT
= 12V