Datasheet

LTC3862
10
3862fc
For more information www.linear.com/LTC3862
pin FuncTions
SENSE2
+
(Pin 13/Pin 11/Pin 13): Positive Inputs to the
Current Comparators. The ITH pin voltage programs the
current comparator offset in order to set the peak current
trip threshold. This pin is normally connected to a sense
resistor in the source of the power MOSFET.
SENSE1
–
(Pin 22/Pin 20/Pin 22): Negative Inputs to the
Current Comparators. This pin is normally connected to
the bottom of the sense resistor.
SENSE2
–
(Pin 14/Pin 12/Pin 14): Negative Inputs to the
Current Comparators. This pin is normally connected to
the bottom of the sense resistor.
SGND (Pin 9/Pin 7/Pin 9): Signal Ground. All feedback and
soft-start connections should return to SGND. For optimum
load regulation, the SGND pin should be kelvin connected
to the PCB location between the negative terminals of the
output capacitors.
SLOPE (Pin 2/Pin 24/Pin 2): This pin programs the gain
of the internal slope compensation. Floating this pin
provides a normalized slope compensation gain of 1.00.
Connecting this pin to 3V8 increases the normalized
slope compensation by 66%, and connecting it to SGND
decreases the normalized slope compensation by 37.5%.
See Applications Information for more details.
SS (Pin 6/Pin 4/Pin 6): Soft-Start Input. For soft-start
operation, connecting a capacitor from this pin to SGND
will clamp the output of the error amp. An internal 5µA
current source will charge the capacitor and set the rate
of increase of the peak switch current of the converter.
SYNC (Pin 11/Pin 9/Pin 11): PLL Synchronization Input.
Applying an external clock between 50kHz and 650kHz
will cause the operating frequency to synchronize to the
clock. SYNC is pulled down by a 50k internal resistor. The
rising edge of the SYNC input waveform will align with the
rising edge of GATE1 in closed-loop operation. A SYNC
signal with an amplitude greater than 1.6V is considered
an active high, while any signal below 0.9V is considered
an active low.
V
IN
(Pin 20/Pin 18/Pin 20): Main Supply Input. A low ESR
ceramic capacitor should be connected between this pin
and SGND.
(SSOP/QFN/TSSOP)