Datasheet

LTC3862
17
3862fc
For more information www.linear.com/LTC3862
operaTion
The LTC3862 uses a constant frequency architecture that
can be programmed over a 75kHz to 500kHz range using
a single resistor from the FREQ pin to ground. Figure 6
illustrates the relationship between the FREQ pin resistance
and the operating frequency.
The operating frequency of the LTC3862 can be approxi
-
mated using the following formula:
R
FREQ
= 5.5096E9(f
OSC
)
–0.9255
A phase-lock loop is available on the LTC3862 to syn-
chronize the internal oscillator to an external clock
source connected to the SYNC pin. Connect a series RC
network from the PLLFLTR pin to SGND to compensate
PLL’
s feedback loop. Typical compensation components
are a 0.01μF capacitor in series with a 10k resistor. The
PLLFLTR pin is both the output of the phase detector and
the input to the voltage controlled oscillator (VCO). The
LTC3862 phase detector adjusts the voltage on the PLL
-
FLTR pin to align the rising edge of GATE1 to the leading
edge of the external clock signal, as shown in Figure 7.
The rising edge of GA
TE2 will depend upon the voltage on
the PHASEMODE pin. The capture range of the LTC3862’s
PLL is 50kHz to 650kHz.
Because the operating frequency of the L
TC3862 can be
programmed using an external resistor, in synchronized
applications, it is recommended that the free-running fre
-
quency (as defined by the external resistor) be set to the
same
value as the synchronized frequency. This results in
a start-up of the IC at approximately the same frequency
as the external clock, so that when the sync signal comes
alive, no discontinuity at the output will be observed. It also
ensures that the operating frequency remains essentially
constant in the event the sync signal is lost. The SYNC
pin has an internal 50k resistor to ground.
Using the CLKOUT and PHASEMODE Pins
in Multi-Phase Applications
The LTC3862 features two pins (CLKOUT and PHASEMODE)
that allow multiple ICs to be daisy-chained together for
higher current multi-phase applications. For a 3- or 4-phase
FREQUENCY (kHz)
100
R
FREQ
(kΩ)
300
1000
3862 F06
10
100
200 1000
900
800700600
500
400
0
Figure 6. FREQ Pin Resistor Value vs Frequency
Figure 7. Synchronization of the LTC3862
to an External Clock Using the PLL
SYNC
10V/DIV
GATE1
10V/DIV
GATE2
10V/DIV
CLKOUT
10V/DIV
2µs/DIVV
IN
= 12V
V
OUT
= 48V 1A
PHASEMODE = SGND
3862 F07
design, the CLKOUT signal of the master controller is con-
nected to the SYNC input of the slave controller in order
to synchronize additional power stages for a single high
current output. The PHASEMODE pin is used to adjust
the phase relationship between channel 1 and channel 2,
as well as the phase relationship between channel 1 and
CLKOUT, as summarized in Table 1. The phases are cal
-
culated relative to the zero degrees, defined as the rising
edge of the GATE1 output. In a 6-phase application the
CLKOUT
pin of the master controller connects to the SYNC
input of the 2nd controller and the CLKOUT pin of the 2nd
controller connects to the SYNC pin of the 3rd controller.