Datasheet

LTC3862
12
3862fc
For more information www.linear.com/LTC3862
operaTion
The Control Loop
The LTC3862 uses a constant frequency, peak current
mode step-up architecture with its two channels operat
-
ing 180 degrees out of phase. During normal operation,
each external MOSFET is turned on when the clock for
that channel sets the PWM latch, and is turned off when
the main current comparator, ICMP, resets the latch. The
peak inductor current at which ICMP trips and resets the
latch is controlled by the voltage on the ITH pin, which is
the output of the error amplifier, EA. The error amplifier
compares the output feedback signal at the V
FB
pin to the
internal 1.223V reference and generates an error signal
at the ITH pin. When the load current increases it causes
a slight decrease in V
FB
relative to the reference voltage,
which causes the EA to increase the ITH voltage until the
average inductor current matches the new load current.
After the MOSFET is turned off, the inductor current flows
through the boost diode into the output capacitor and load,
until the beginning of the next clock cycle.
Cascaded LDOs Supply Power to the Gate Driver and
Control Circuitry
The LTC3862 contains two cascaded PMOS output stage
low dropout voltage regulators (LDOs), one for the gate
drive supply (INTV
CC
) and one for the low voltage analog
and digital control circuitry (3V8). A block diagram of this
power supply arrangement is shown in Figure 1.
The Gate Driver Supply LDO (INTV
CC
)
The 5V output (INTV
CC
) of the first LDO is powered from
V
IN
and supplies power to the power MOSFET gate driv-
ers. The INTV
CC
pin should be bypassed to PGND with a
minimum of 4.7μF of ceramic capacitance (X5R or better),
placed as close as possible to the IC pins. If two power
MOSFETs are connected in parallel for each channel in
order to increase the output power level, or if a single
MOSFET with a Q
G
greater than 50nC is used, then it is
recommended that the bypass capacitance be increased
to a minimum of 10μF.
An undervoltage lockout (UVLO) circuit senses the INTV
CC
regulator output in order to protect the power MOSFETs
from operating with inadequate gate drive. For the LTC3862
the rising UVLO threshold is typically 3.3V and the hyster
-
esis is typically 400mV. The LTC3862 was optimized for
logic-level power MOSFETs and applications where the
output voltage is less than 50V to 60V. For applications
requiring standard threshold power MOSFETs, please refer
to the LTC3862-1 data sheet.
–
+
SGND
R2 R1
1.223V
LTC3862
INTV
CC
3V8
GATE
–
+
SGND
R4
R3
1.223V
P-CH
P-CH
ANALOG
CIRCUITS
LOGIC
INTV
CC
V
IN
C
IN
C
VCC
C
3V8
3862 F01
PGND
3V8
SGND
NOTE: PLACE C
VCC
AND C
3V8
CAPACITORS AS CLOSE AS POSSIBLE TO DEVICE PINS
Figure 1. Cascaded LDOs Provide Gate Drive and Control Circuitry Power