Datasheet

LTC3862-1
12
38621f
OPERATION
The Control Loop
The LTC3862-1 uses a constant frequency, peak current
mode step-up architecture with its two channels operat-
ing 180 degrees out of phase. During normal operation,
each external MOSFET is turned on when the clock for
that channel sets the PWM latch, and is turned off when
the main current comparator, ICMP, resets the latch. The
peak inductor current at which ICMP trips and resets the
latch is controlled by the voltage on the ITH pin, which is
the output of the error amplifi er, EA. The error amplifi er
compares the output feedback signal at the V
FB
pin to the
internal 1.223V reference and generates an error signal
at the ITH pin. When the load current increases it causes
a slight decrease in V
FB
relative to the reference voltage,
which causes the EA to increase the ITH voltage until the
average inductor current matches the new load current.
After the MOSFET is turned off, the inductor current fl ows
through the boost diode into the output capacitor and load,
until the beginning of the next clock cycle.
Cascaded LDOs Supply Power to the Gate Driver and
Control Circuitry
The LTC3862-1 contains two cascaded PMOS output stage
low dropout voltage regulators (LDOs), one for the gate
drive supply (INTV
CC
) and one for the low voltage analog
and digital control circuitry (3V8). A block diagram of this
power supply arrangement is shown in Figure 1.
The Gate Driver Supply LDO (INTV
CC
)
The 10V output (INTV
CC
) of the fi rst LDO is powered from
V
IN
and supplies power to the power MOSFET gate driv-
ers. The INTV
CC
pin should be bypassed to PGND with a
minimum of 4.7F of ceramic capacitance (X5R or better),
placed as close as possible to the IC pins. If two power
MOSFETs are connected in parallel for each channel in
order to increase the output power level, or if a single
MOSFET with a Q
G
greater than 50nC is used, then it is
recommended that the bypass capacitance be increased
to a minimum of 10F.
An undervoltage lockout (UVLO) circuit senses the INTV
CC
regulator output in order to protect the power MOSFETs from
operating with inadequate gate drive. For the LTC3862-1
the rising UVLO threshold is typically 7.5V and the hys-
teresis is typically 500mV. The LTC3862-1 was optimized
for high voltage power MOSFETs and applications. For
applications requiring logic-level power MOSFETs, please
refer to the LTC3862 data sheet.
Figure 1. Cascaded LDOs Provide Gate Drive and Control Circuitry Power
–
+
SGND
R2 R1
1.223V
LTC3862-1
INTV
CC
3V8
GATE
–
+
SGND
R4
R3
1.223V
P-CH
P-CH
ANALOG
CIRCUITS
LOGIC
INTV
CC
V
IN
C
IN
C
VCC
C
3V8
38621 F01
PGND
3V8
SGND
NOTE: PLACE C
VCC
AND C
3V8
CAPACITORS AS CLOSE AS POSSIBLE TO DEVICE PINS