Datasheet

LTC3861
9
3861fa
For more information www.linear.com/LTC3861
VSNSOUT1 (Pin 5), VSNSOUT2 (Pin 6): Differential Am-
plifier Output.
Connect to FB1, FB2 with a compensation
network for remote V
OUT
sensing.
FREQ (Pin 12): Frequency Set/Select Pin. This pin sources
20µA current. If CLKIN is high or floating, then a resistor
between this pin and SGND sets the switching frequency. If
CLKIN is low, the logic state of this pin selects an internal
600kHz or 1MHz preset frequency.
CLKIN (Pin 13): External Clock Synchronization Input.
Applying an external clock between 250kHz to 2.25MHz
will cause the switching frequency to synchronize to the
clock. CLKIN is pulled high to V
CC
by a 50k internal resis-
tor. The rising edge of the CLKIN input waveform will align
with
the rising edge of PWM1 in closed-loop operation. If
CLKIN is high or floating, a resistor from the FREQ pin to
SGND sets the switching frequency. If CLKIN is low, the
FREQ pin logic state selects an internal 600kHz or 1MHz
preset frequency.
CLKOUT (Pin 14): Digital Output Used for Daisychaining
Multiple LTC3861 ICs in Multiphase Systems. The PHSMD
pin voltage controls the relationship between CH1 and CH2
as well as between CH1 and CLKOUT. When both RUN pins
are driven
low, the CLKOUT pin is actively pulled up to V
CC
.
PHSMD (Pin 15): Phase Mode Pin. The PHSMD pin volt-
age programs
the phase relationship between CH1 and
CH2 rising PWM signals, as well as the phase relationship
between CH1 PWM signal and CLKOUT. Floating this pin
or connecting it to either V
CC
or SGND changes the phase
relationship between CH1, CH2 and CLKOUT.
SGND (Pins 21, 26, Exposed Pad Pin 37): Signal Ground.
Pins 21, 26, and 37 are electrically connected internally.
The exposed pad must be soldered to the PCB ground
for rated thermal performance. All soft-start, small-signal
and compensation components should return to SGND.
ISNS1N (Pin 24), ISNS2N (Pin 23): Current Sense Am
-
plifier (–) Input. The
(–)
input to the current amplifier is
normally connected to the respective V
OUT
at the inductor.
ISNS1P (Pin 25), ISNS2P (Pin 22): Current Sense Ampli-
fier (+) Input. The
(+) input to the current sense amplifier
is normally connected to the midpoint of the inductor’s
parallel RC sense circuit or to the node between the induc
-
tor and sense resistor if using a discrete sense resistor.
I
LIM1
(Pin 27), I
LIM2
(Pin 20): Current Comparator Sense
Voltage Limit Selection Pin. Connect a resistor from this
pin to SGND. This pin sources 20µA. The resultant voltage
sets the threshold for over
current protection.
RUN1 (Pin 28), RUN2 (Pin 19): Run Control Inputs. A
voltage above 2.25V on either pin turns on the IC. How
-
ever, forcing either of these pins below 2V causes the
IC
to shut down that particular channel. There are 1.5µA
pull-up currents for these pins.
PWM1 (Pin 29), PWM2 (Pin 18): (Top) Gate Signal Out
-
put. This signal goes to the PW
M or top gate input of the
external gate driver or integrated driver MOSFET. This is
a three-state compatible output.
PWMEN1 (Pin 30), PWMEN2 (Pin 17): Enable Pin for
Non-Three-State compatible
drivers. This pin has an in-
ternal open-drain pull-up to V
CC
. An external resistor to
SGND is required. This pin is low when the corresponding
PWM pin is high impedance.
PGOOD1 (Pin 31), PGOOD2 (Pin 16): Power Good Indi
-
cator Output for Each Channel. Open-drain logic out that
is
pulled to SGND when either channel output exceeds a
±10% regulation window, after the internal 30µs power
bad mask timer expires.
I
AVG
(Pin 32): Average Current Output Pin. A capacitor tied
to ground from this pin stores a voltage proportional to the
instantaneous average
current of the master when multiple
outputs are paralleled together in a master-slave configu
-
ration. Only the master phase contributes information to
this average through an internal resistor when in current
sharing mode. The I
AVG
pin ignores channels configured for
independent operation, hence the pin should be connected
to SGND when the controller drives independent outputs.
VINSNS (Pin 34): V
IN
Sense Pin. Connects to the V
IN
power supply to provide line feedforward compensation.
A change in V
IN
immediately modulates the input to the
PWM comparator and changes the pulse width in an in-
versely proportional
manner, thus bypassing the feedback
loop and providing excellent transient line regulation. An
external lowpass filter can be added to this pin to prevent
noisy signals from affecting the loop gain.
pin FuncTions