Datasheet

LTC3861
32
3861fa
For more information www.linear.com/LTC3861
applicaTions inFormaTion
minimum spacing between them. If DCR sensing is
used, place the top resistor (Figure 6b, R1) close to
the switching node.
4. The input capacitor should be kept as close as possible
to the power MOSFETs. The loop from the input capaci-
tor’s positive terminal, through the MOSFETs and back
to the input capacitor’s negative terminal should also
be as small as possible.
5. If using discrete drivers and MOSFETs, check the stress
on the MOSFETs by independently measuring the drain-
to-source voltages directly across the device terminals.
Beware of inductive ringing that could exceed the
maximum voltage rating of the MOSFET. If this ringing
cannot be avoided and exceeds the maximum rating of
the device, choose a higher voltage rated MOSFET.
6. When cascading multiple LTC3861 ICs, minimize
the capacitive load on the CLKOUT pin to minimize
phase error. Kelvin all the LTC3861 IC grounds to the
same
point, typically SGND of the IC containing the
master.
Typical applicaTions
Dual Phase 1.2V/45A Converter with Delta 45A Power Block, f
SW
= 400kHz
V
OUT
1.2V/45A
C
OUT1
100µF × 4
6.3V
22µF
16V
22µF
16V
22µF
16V
22µF
16V
C
OUT2
: SANYO 2R5TPE330M9
C
OUT1
: MURATA GRM32ER60J107ME20
C
OUT2
330µF× 6
2.5V
0.22µF
0.22µF
30.9k
V
CC
V
CC
49.9k
3.4k
1.5nF
LTC3861
FB1
COMP1
VSNSP1
VSNSN1
VSNSOUT1
VSNSOUT2
VSNSN2
VSNSP2
COMP2
FB2
+CS1
V
IN1
PWM1
GND
PWM2
V
IN2
+CS2
–CS1
GND
V
OUT1
+7V
V
OUT2
GND
–CS2
RUN1
I
LIM1
SGND
ISNS1P
ISNS1N
ISNS2N
ISNS2P
SGND
I
LIM2
RUN2
V
CC
SS1
VINSNS
CONFIG
I
AVG
PGOOD1
PWMEN1
PWM1
SS2 FREQ CLKIN CLKOUT PHSMD PGOOD2 PWMEN2 PWM2
RUN1
RUN1
V
CC
V
OUT
V
CC
5V
100k
10k
110Ω
6.8nF
270pF
10k
10k
1µF
V
IN
7V TO 14V
TEMP1
TEMP2
D12S1-
R845A
SS1
SS1
V
IN
C
IN
180µF
3861 TA02
100pF
4.7µF