Datasheet

LTC3861
30
3861fa
For more information www.linear.com/LTC3861
applicaTions inFormaTion
When the controller is operating in continuous mode
the duty cycles for the top and bottom MOSFETs are
given by:
Main Switch Duty Cycle
V
V
Synchronous S
OUT
IN
=
wwitch Duty Cycle
VV
V
IN OUT
IN
–
=
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
P
V
V
IR
V
I
MAIN
OUT
IN
MAX DS ON
IN
MAX
=
()
++
2
2
1
2
()
(
()
δ
RRC
VV V
DR MILLER
CC TH IL TH IL
)( ) •
–
() ()
11
+
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥⎥
=
−
+
()
( )( )
()
f
P
VV
V
IR
SYNC
IN OUT
IN
MAX DS N
2
0
1 δ
where δ is the temperature dependency of R
DS(ON)
, R
DR
is the effective top driver resistance, V
IN
is the drain po-
tential and the change in drain potential in the particular
application.
V
TH(IL)
is the data sheet specified typical gate
threshold voltage specified in the power MOSFET data sheet
at the specified drain current. C
MILLER
is the calculated
capacitance using the gate charge curve from the MOSFET
data sheet and the technique previously described.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R
DS(ON)
vs temperature curve. Typical
values for δ range from 0.005/°C to 0.01/°C depending
on the particular MOSFET used.
Multiple MOSFETs can be used in parallel to lower R
DS(ON)
and meet the current and thermal requirements if desired.
Suitable drivers such as the LTC4449 are capable of driv
-
ing large gate capacitances without significantly slowing
transition times. In fact, when driving MOSFETs with very
low gate charge, it is sometimes helpful to slow down
the drivers by adding small gate resistors (5Ω or less)
to reduce noise and EMI caused by the fast transitions
MOSFET Driver Selection
Gate driver ICs, DrMOSs and power blocks
with an interface
compatible with the LTC3861’s three-state PWM outputs
or the LTC3861’s PWM/PWMEN outputs can be used.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power. It is often useful
to analyze individual losses to determine what is limiting
the efficiency and which change would produce the most
improvement. Percent efficiency can be expressed as:
%Efficiency = 100% - (L1 + L2 + L3 + …)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although
all dissipative elements in the system produce
losses, three main sources usually account for most of the
losses in LTC3861 applications: 1) I
2
R losses, 2) topside
MOSFET transition losses, 3) gate drive current.
1. I
2
R losses occur mainly in the DC resistances of the
MOSFET, inductor, PCB routing, and input and output
capacitor ESR. Since each MOSFET is only on for part
of the cycle, its on-resistance is effectively multiplied
by the percentage of the cycle it is on. Therefore in high
step-down ratio applications the bottom MOSFET should
have a much lower R
DS(ON)
than the top MOSFET. It
is crucial that careful attention is paid to the layout of
the power path on the PCB to minimize its resistance.
In
a 2-phase, 1.2V output, 60A system, 1mΩ of PCB
resistance at the output costs 5% in efficiency.
2. Transition losses apply only to the topside MOSFET but
in 12V input applications are a very significant source
of loss. They can be minimized by choosing a driver
with very low drive resistance and choosing a MOSFET
with low Q
G
, R
G
and C
RSS
.
3. Gate drive current is equal to the sum of the top and
bottom MOSFET gate charges multiplied by the fre-
quency of operation. However, many drivers employ a
linear
regulator to reduce the input voltage to a lower
gate drive voltage. This multiplies the gate loss by that
step down ratio. In high frequency applications it may
be worth using a secondary user supplied rail for gate
drive to avoid the linear regulator.