Datasheet

LTC3861
19
3861fa
For more information www.linear.com/LTC3861
applicaTions inFormaTion
The programmed current limit must be low enough to
ensure that the inductor never saturates and high enough
to allow increased current during transient conditions and
allow margin for DCR variation.
For example, if:
I
SAT
= 2.2 • I
OUT
and
I
MAX
= 1.6 • I
OUT
A reasonable I
LIMIT
would be:
I
LIMIT
= 1.8 • I
OUT
If the sensed inductor current exceeds current limit for
128 consecutive clock cycles, the IC will three-state the
PWM outputs, reset the soft-start timer and wait 32768
switching cycles before attempting to return the output
to regulation.
The current limit is programmed using a resistor from the
I
LIM
pin to SGND. The I
LIM
pin sources 20µA to generate
a voltage corresponding to the current limit. The current
sense circuit has a voltage gain of 18.5 and a zero current
level of 500mV. Therefore, the current limit resistor should
be set using the following equation:
R
ILIM
=
18.5 •I
LIMIT
–
PHASE
• R
SENSE
+ 0.5V
20µA
In multiphase applications only one current limit resistor
should be used per LTC3861. The I
LIM2
pin should be tied
to V
CC
. Internal logic will then cause channel 2 to use the
same current limit levels as channel 1. If an LTC3861 has
a slave and an independent, then both I
LIM
pins must be
independently set to the right voltage.
Inductor Core Selection
Once the value of L is known, the type of inductor must be
selected. High efficiency converters generally cannot afford
the core losses found in low cost powdered iron cores,
forcing the use of more expensive ferrite or molypermalloy
cores. Also, core losses decrease as inductance increases.
Unfortunately, increased inductance requires more turns
of wire, larger inductance and larger copper losses.
Ferrite designs have very low core loss and are preferred at
high switching frequencies. However, these core materials
exhibit “hard” saturation, causing an abrupt reduction in the
inductance when the peak current capability is exceeded.
Do not allow the core to saturate!
C
IN
Selection
The input bypass capacitor in an LTC3861 circuit is com-
mon to
both channels. The input bypass capacitor needs
to
meet these conditions: its ESR must be low enough to
keep the
supply drop low as the top MOSFETs turn on, its
RMS
current capability must be adequate to withstand the
ripple current at the input, and the capacitance must be
large enough to maintain the input voltage until the input
supply can make up the difference. Generally, a capacitor
(particularly a non-ceramic type) that meets the first two
parameters will have far more capacitance than is required
to keep capacitance-based droop under control.
The input capacitor’s voltage rating should be at least 1.4
times the maximum input voltage. Power loss due to ESR
occurs not only as I
2
R dissipation in the capacitor itself,
but also in overall battery efficiency. For mobile applica-
tions, the input capacitors should store adequate charge
to
keep the peak battery current within the manufacturer’s
specifications.
The input capacitor RMS current requirement is simpli
-
fied by the multiphase architecture and its impact on the
worst-case
RMS current drawn through the input network
(battery/fuse/capacitor). It can be shown that the worst-
case RMS current occurs when only one controller is
operating. The controller with the highest (V
OUT
)(I
OUT
)
product needs to be used to determine the maximum
RMS current
requirement.
Increasing the output current