Datasheet

LTC3860
26
3860fc
APPLICATIONS INFORMATION
Effi ciency Considerations
The effi ciency of a switching regulator is equal to the
output power divided by the input power. It is often useful
to analyze individual losses to determine what is limiting
the effi ciency and which change would produce the most
improvement. Percent effi ciency can be expressed as:
%Effi ciency = 100% - (L1 + L2 + L3 + …)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the system produce
losses, three main sources usually account for most of the
losses in LTC3860 applications: 1) I
2
R losses, 2) topside
MOSFET transition losses, 3) gate drive current.
1. I
2
R losses occur mainly in the DC resistances of the
MOSFET, inductor, PCB routing, and input and output
capacitor ESR. Since each MOSFET is only on for part
of the cycle, its on-resistance is effectively multiplied
by the percentage of the cycle it is on. Therefore in high
step-down ratio applications the bottom MOSFET should
have a much lower R
DS(ON)
than the top MOSFET. It
is crucial that careful attention is paid to the layout of
the power path on the PCB to minimize its resistance.
In a 2-phase, 1.2V output, 60A system, 1mΩ of PCB
resistance at the output costs 5% in effi ciency.
2. Transition losses apply only to the topside MOSFET but
in 12V input applications are a very signifi cant source
of loss. They can be minimized by choosing a driver
with very low drive resistance and choosing a MOSFET
with low Q
G
, R
G
and C
RSS
.
3. Gate drive current is equal to the sum of the top and
bottom MOSFET gate charges multiplied by the fre-
quency of operation. However, many drivers employ a
linear regulator to reduce the input voltage to a lower
gate drive voltage. This multiplies the gate loss by that
step down ratio. In high frequency applications it may
be worth using a secondary user supplied rail for gate
drive to avoid the linear regulator.
Other sources of loss include body or Schottky diode
conduction during the driver dependent non-overlap time
and inductor core losses.
Design Example
As a design example, consider a 2-phase application
where V
IN
= 12V, V
OUT
= 1.2V, I
LOAD
= 50A and f
SWITCH
=
600kHz. Assume that a secondary 5V supply is available
for the LTC3860 V
CC
supply.
The inductance value is chosen based on a 30% ripple
assumption. Each channel supplies an average 25A to the
load resulting in 7.5A peak-peak ripple:
ΔI
L
=
V
OUT
•1–
V
OUT
V
IN
⎛
⎝
⎜
⎞
⎠
⎟
f•L
A 240nH inductor per phase will create 7.5A peak-to-peak
ripple. A 0.3μH inductor with a DCR of 0.7mΩ typical
is selected from the Vishay IHLP5050FD-01 series.
Connect CLKIN to SGND and FREQ to V
CC
to select
600kHz operation. Setting I
LIMIT
= 50A per phase leaves
plenty of headroom for transient conditions while still
adequately protecting against inductor saturation. This
corresponds to:
R
ILIM
=
18.5 • 50A • 0.7mΩ+0.53V
20µA
= 58.8k
Ω
Choose 59.0kΩ.
For the DCR sense fi lter network, we can choose R = 2.0k
and C = 220nF to match the L/DCR time constant of the
inductor.
A loop crossover frequency of 100kHz provides good
transient performance while still being well below the
switching frequency of the converter. Four 330μF 9mΩ
POSCAPs are chosen for the output capacitors to maintain
supply regulation during severe transient conditions and
to minimize output voltage ripple.
The following compensation values (Figure 12) were
determined empirically:
R1 = 10k
R2 = 6.04k
R3 = 698
C1 = 680pF
C2 = 47pF
C3 = 390pF