Datasheet

LTC3859A
25
3859af
applicaTions inForMaTion
In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (V
OUT
)/(V
IN
). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current of one channel must be used. The
maximum RMS capacitor current is given by:
C
IN
Required I
RMS
≈
I
MAX
V
IN
V
OUT
( )
V
IN
− V
OUT
( )




1/2
(1)
This formula has a maximum at V
IN
= 2V
OUT
, where I
RMS
= I
OUT
/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3859A, ceramic capacitors
can also be used for C
IN
. Always consult the manufacturer
if there is any question.
The benefit of the LTC3859A 2-phase operation can be cal-
culated by using Equation (1) for the higher power controller
and then calculating the loss that would have resulted if
both controller channels switched on at the same time.
The total RMS power lost is lower when both controllers
are operating due to the reduced overlap of current pulses
required through the input capacitor’s ESR. This is why
the input capacitor’s requirement calculated above for the
worst-case controller is adequate for the dual controller
design. Also, the input protection fuse resistance, battery
resistance, and PC board trace resistance losses are also
reduced due to the reduced peak currents in a 2-phase
system. The overall benefit of a multiphase design will
only be fully realized when the source impedance of the
power supply/battery is included in the efficiency testing.
The drains of the top MOSFETs should be placed within
1cm of each other and share a common C
IN
(s). Separat-
ing the drains and C
IN
may produce undesirable voltage
and current resonances at V
IN
.
A small (0.1µF to 1µF) bypass capacitor between the chip
V
IN
pin and ground, placed close to the LTC3859A, is also
suggested. A small (1Ω to 10Ω) resistor placed between
C
IN
(C1) and the V
IN
pin provides further isolation between
the two channels.
The selection of C
OUT
is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (DV
OUT
) is approximated by:
DV
OUT
≈ DI
L
ESR+
1
8fC
OUT






where f is the operating frequency, C
OUT
is the output
capacitance and DI
L
is the ripple current in the inductor.
The output ripple is highest at maximum input voltage
since DI
L
increases with input voltage.
Setting Output Voltage
The LTC3859A output voltages are each set by an external
feedback resistor divider carefully placed across the output,
as shown in Figure 5. The regulated output voltages are
determined by:
V
OUT, BUCK
= 0.8V 1+
R
B
R
A






V
OUT, BOOST
= 1.2V 1+
R
B
R
A






To improve the frequency response, a feedforward ca-
pacitor, C
FF
, may be used. Great care should be taken to
route the V
FB
line away from noise sources, such as the
inductor or the SW line.
Figure 5. Setting Output Voltage
3859A F05
1/3 LTC3859A
V
FB
R
B
C
FF
R
A
V
OUT