Datasheet

LTC3859A
17
3859af
operaTion
Frequency Selection and Phase-Locked Loop
(FREQ and PLLIN/MODE Pins)
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3859A’s controllers
can be selected using the FREQ pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to SGND, tied to
INTV
CC
, or programmed through an external resistor. Tying
FREQ to SGND selects 350kHz while tying FREQ to INTV
CC
selects 535kHz. Placing a resistor between FREQ and
SGND allows the frequency to be programmed between
50kHz and 900kHz.
A phase-locked loop (PLL) is available on the LTC3859A
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
LTC3859A’s phase detector adjusts the voltage (through
an internal lowpass filter) of the VCO input to align the
turn-on of controller 1’s external top MOSFET to the ris-
ing edge of the synchronizing signal. Thus, the turn-on
of controller 2’s external top MOSFET is 180 degrees out
of phase to the rising edge of the external clock source.
The VCO input voltage is pre-biased to the operating
frequency set by the FREQ pin before the external clock
is applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of TG1. The ability to
pre-bias the loop filter allows the PLL to lock in rapidly
without deviating far from the desired frequency.
The typical capture range of the LTC3859A’s phase-locked
loop is from approximately 55kHz to 1MHz, with a guar-
antee over all manufacturing variations to be between
75kHz and 850kHz. In other words, the LTC3859A’s PLL
is guaranteed to lock to an external clock source whose
frequency is between 75kHz and 850kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling).
Boost Controller Operation When V
IN
> V
OUT
When the input voltage to the boost channel rises above
its regulated V
OUT
voltage, the controller can behave
differently depending on the mode, inductor current and
V
IN
voltage. In forced continuous mode, the loop works
to keep the top MOSFET on continuously once V
IN
rises
above V
OUT
. An internal charge pump delivers current to
the boost capacitor from the BOOST3 pin to maintain a
sufficiently high TG voltage. (The amount of current the
charge pump can deliver is characterized by two curves
in the Typical Performance Characteristics section.)
In pulse-skipping mode, if V
IN
is between 100% and
110% of the regulated V
OUT
voltage, TG3 turns on if the
inductor current rises above approximately 3% of the
programmed I
LIM
current. If the part is programmed in
Burst Mode operation under this same V
IN
window, then
TG3 turns on at the same threshold current as long as
the chip is awake (one of the buck channels is awake and
switching). If both buck channels are asleep or shut down
in this V
IN
window, then TG3 will remain off regardless of
the inductor current.
If V
IN
rises above 110% of the regulated V
OUT
voltage in
any mode, the controller turns on TG3 regardless of the
inductor current. In Burst Mode operation, however, the
internal charge pump turns off if the entire chip is asleep
(the two buck channels are asleep or shut down). With
the charge pump off, there would be nothing to prevent
the boost capacitor from discharging, resulting in an
insufficient TG voltage needed to keep the top MOSFET
completely on. The charge pump turns back on when the
chip wakes up, and it remains on as long as one of the
buck channels is actively switching.
Boost Controller at Low SENSE Pin Common Voltage
The current comparator of the boost controller is powered
directly from the SENSE3
+
pin and can operate to voltages
as low as 2.5V. Since this is lower than the V
BIAS
UVLO of
the chip, V
BIAS
can be connected to the output of the boost
controller, as illustrated in the typical application circuit
in Figure 12. This allows the boost controller to handle
input voltage transients down to 2.5V while maintaining
output voltage regulation. If the SENSE3
+
rises back
above 2.5V, the SS3 pin will be released initiating a new
soft-start sequence.