Datasheet

LTC3857
27
3857fd
APPLICATIONS INFORMATION
Figure 11. Recommended Printed Circuit Layout Diagram
C
B2
C
B1
R
PU1
PGOOD1
V
PULL-UP
C
INTVCC
C
IN
D1
1µF
CERAMIC
M1 M2
M3
M4
D2
C
VIN
V
IN
R
IN
L1
L2
C
OUT1
V
OUT1
GND
V
OUT2
3857 F11
C
OUT2
R
SENSE
R
SENSE
R
PU2
PGOOD2
V
PULL-UP
f
IN
1µF
CERAMIC
I
TH1
V
FB1
SENSE1
+
SENSE1
–
FREQ
SENSE2
–
SENSE2
+
V
FB2
I
TH2
TRACK/SS2
TRACK/SS1
PGOOD2
PGOOD1
TG1
SW1
BOOST1
BG1
V
IN
PGND
EXTV
CC
INTV
CC
BG2
BOOST2
SW2
TG2
ILIM
PHASMD
CLKOUT
PLLIN/MODE
RUN1
RUN2
SGND
+
+
+
LTC3857
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 11. Figure 12 illustrates the current
waveforms present in the various branches of the 2-phase
synchronous regulators operating in the continuous mode.
Check the following in your layout:
1. Are the top N-channel MOSFETs MTOP1 and MTOP2
located within 1cm of each other with a common drain
connection at C
IN
? Do not attempt to split the input
decoupling for the two channels as it can cause a large
resonant loop.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of C
INTVCC
must return to the combined C
OUT
(–) ter-
minals. The path formed by the top N-channel MOSFET,
Schottky diode and the C
IN
capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible
to the (–) terminals of the input capacitor by placing
the capacitors next to each other and away from the
Schottky loop described above.
3. Do the LTC3857 V
FB
pins’ resistive dividers connect to
the (+) terminals of C
OUT
? The resistive divider must be
connected between the (+) terminal of C
OUT
and signal
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).