Datasheet

LTC3856
22
3856f
applicaTions inForMaTion
The peak-to-peak MOSFET gate drive levels are set by the
voltage, V
CC
, requiring the use of logic-level threshold
MOSFETs in most applications. Pay close attention to the
BV
DSS
specification for the MOSFETs as well; many of the
logic-level MOSFETs are limited to 30V or less. Selection
criteria for the power MOSFETs include the on-resistance,
R
DS(ON)
, input capacitance, input voltage and maximum
output current. MOSFET input capacitance is a combination
of several components but can be taken from the typical
gate charge curve included on most data sheets (Figure 9).
The curve is generated by forcing a constant input current
into the gate of a common source, current source loaded
stage, then plotting the gate voltage versus time.
mode, the duty cycles for the top and bottom MOSFETs
are given by:
Main SwitchDuty Cycle
V
V
Synchronous Switc
OUT
IN
=
hhDuty Cycle
V V
V
IN OUT
IN
=






–
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
P
V
V
I
N
R
V
MAIN
OUT
IN
MAX
DS ON
IN
=






+
( )
+
( )
2
1 δ
( )
22
2
1 1
I
N
R C
V V
MAX
DR MILLER
CC TH IL






( )( )
+
•
–
( )
VV
f
P
V V
V
I
N
TH IL
SYNC
IN OUT
IN
MAX
( )
•
–








=






+
( )
2
1 δ R
DS ON( )
where N is the number of output stages, δ is the tem-
perature dependency of R
DS(ON)
, R
DR
is the effective top
driver resistance (approximately 2Ω at V
GS
= V
MILLER
),
V
IN
is the drain potential and the change in drain poten-
tial in the particular application. V
TH(IL)
is the data sheet
specified typical gate threshold voltage specified in the
power MOSFET data sheet at the specified drain current.
C
MILLER
is the calculated capacitance using the gate charge
curve from the MOSFET data sheet and the technique just
described.
Both MOSFETs have I
2
R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V
IN
< 20V,
the high current efficiency generally improves with larger
MOSFETs, while for V
IN
> 20V, the transition losses rapidly
increase to the point that the use of a higher R
DS(ON)
device
with lower C
MILLER
actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low, or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
+
–
V
DS
V
IN
3856 F09
V
GS
MILLER EFFECT
Q
IN
a b
C
MILLER
= (Q
B
– Q
A
)/V
DS
V
GS
V
+
–
Figure 9. Gate Charge Characteristic
The initial slope is the effect of the gate-to-source and
the gate-to-drain capacitance. The flat portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line is
due to the drain-to-gate accumulation capacitance and
the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is flat) is specified for a given V
DS
drain
voltage, but can be adjusted for different V
DS
voltages by
multiplying the ratio of the application V
DS
to the curve
specified V
DS
values. A way to estimate the C
MILLER
term is to take the change in gate charge from points
a and b on a manufacturer’s data sheet and divide by
the stated V
DS
voltage specified. C
MILLER
is the most
important selection criteria for determining the transition
loss term in the top MOSFET but is not directly specified
on MOSFET data sheets. C
RSS
and C
OS
are specified
sometimes but definitions of these parameters are not
included. When the controller is operating in continuous